C3 Critical Cleanliness Control

C3 Critical Cleanliness Control Description:

Localized Electronics Cleanliness Tester and Residue Extractor

The information gathered when using the C3 is intended to provide a measure of the cleanliness of a localized region of a circuit board. In addition, the C3 extracts a sample of the effluent from that localized region that can be used in further ionic analysis (such as ion chromatography).

Simple “Clean” / “Dirty” analysis is performed using the C3 on-board measurement system. If more detailed analysis of residues is required, the extracted solution can be analyzed using more sophisticated techniques such as ion chromatography.

The C3 on-board measurement system uses a sacrificial circuit board electrode, immersed in the extracted solution, to measure the electrical conductivity of the solution. By applying a known bias (10 volts) across the electrode terminals, a leakage current between the traces can be measured.

Using the results from both SIR (surface insulation resistance) and ion chromatography testing, a leakage current of 250 μA has been established to identify when a current leakage event has occurred. These test parameter settings (250 μA and 120 sec.) produce relatively sensitive C3 tests and are commonly used on higher reliability electronics (e.g. IPC Class II and III). Another commonly used set of C3 test parameters is 500 μA and 60 seconds. These settings are used on electronics for less demanding applications and environments (e.g. IPC Class I).

The design of the C3 assumes that the more corrosive or conductive the extracted residue, the quicker a current leakage event occurs. The less corrosive or conductive the residue, the longer it will take to reach a 250 μA event.

The C3 system measures the time taken to reach a 250 μA current leakage event. Extensive testing has shown that C3 timing results that achieve the 250 μA event in less than 120 seconds correlate to residues that exceed the ionic contamination limits set forth by Foresite, Inc. Such results are identified as unacceptable and that region of thecircuit board is considered “Dirty”. Timing events that take longer than 120 seconds to achieve a 250 μA current leakage event correlate to acceptable residue levels and that region of the board is considered “Clean”.