D32PRO - scalable & royalty-free 32-bit CPU

D32PRO - scalable & royalty-free 32-bit CPU Description:

The D32PRO is a royalty free, silicon proven, high performance soft core of a single-chip 32-bit embedded controller, with Floating Point Coprocessor. Thanks to its increased code density, the D32PRO meets power and size requirements of new connected devices. That’s why both power and performance of this IP Core predestine it as a real alternative for ARM Cortex M0/M0+/M1/M3 in the deeply embedded market and especially for emerging market of connected devices (IoT). Responding to continuing demands for less power drain in system-on-chip (SoC) designs, DCD has developed the instruction set aimed at reducing the size of system's instruction memory. The D32PRO is aimed at low-power always on/always listening systems and those with less demanding clock frequencies such as Bluetooth Low Energy. Nevertheless the core is perfect for embedded systems that require greater computational performance and system complexity by supporting dual- and multi-core systems as well as improved code density. DCD’s IP Core is fully customizable - it is delivered in an exact configuration to meet customer’s requirements. The D32PRO is offered with great variety of peripherals, like USB, SPI, LCD, HDLC, UART, Ethernet MAC, CAN, LIN, RTC and many more – ready to be implemented with the CPU. The D32PRO is delivered with fully automated test bench and complete set of tests, allowing easy package validation at each stage of SoC design.

Performance

The D32PRO is a silicon proven, royalty-free 32-bit CPU

• UMC 110nm, 1.2V, @150MHz, 128kB code
• Consumes as little as 7µW/MHz (90LP process, minimal configuration) 
• An area of under 10.6 K gates (0.029 mm2)

Key Features

D32PRO offers Complete Software Development Platform

● Configurable 32-bit Harvard architecture
● Performance up to 1.52 / 2.67 DMIPS/MHz and 2.59 CoreMarks/MHz
● Small footprint starting at 10.6k/6.8k ASIC gates
● Very high clock frequency up to 1 GHz in modern ASIC technologies
● Fifteen 32-bit general Purpose registers
● ASIC Silicon proven architecture
● Up to 256 MB of Code Space with encrypted bootloader
● Up to 256 MB of Data Space
● Built-in configurable Floating Point co-processor using dedicated instructions
● Configurable 32-bit hardware multiplier
● Configurable 32-bit hardware divider
● Configurable 32-bit hardware shifter
● Low power consumption by Advanced Power Management Unit
   ○ Advanced Power management mode
   ○ Switchback feature
   ○ Stop mode
● Configurable Interrupt Controller
  ○ Non Maskable Interrupt
  ○ Up to 16 priority levels
  ○ Up to 32 external interrupt sources
● System clock controller supporting
  ○ Phase Locked Loops (PLL)
  ○ external clock generator
  ○ on-chip clock oscillator
● DoCD™ on chip debug unit
  ○ Processor execution control
       ○ Run, Halt
       ○ Step into instruction
       ○ Skip instruction
  ○ Read-write all processor contents
       ○ System Space
       ○ Program Memory Space
       ○ Data Memory Space
       ○ Peripherals Space
  ○ Code execution breakpoints
       ○ up to eight real-time PC breakpoints
       ○ unlimited number of real-time OPCODE breakpoints
  ○ Hardware execution watch-points at
       ○ Data Memory Space
       ○ Program Memory Space
       ○ Peripherals Space
       ○ System Space
  ○ Hardware watch-points activated at a certain
      ○ address by any write into any Space
      ○ address by any read from Space
      ○ address by write into space a required data
      ○ address by read from space a required data
  ○ Hardware watch-point windows activated at a certain
     ○ Start/stop address by any write into any Space
     ○ Start/stop address by any read from Space
     ○ Start/stop address by write into space a required data
     ○ Start/stop address by read from space a required data
   ○ 2-wire high-speed communication interface
● Ultimate dense code
● Great variety of peripherals
● AHB-Lite interface ready
● Rapid & easy development with ready to use tools
● Customization friendly with GUI
● Patent pending architecture

Applications

Comprehensible and clearly defined licensing methods without royalty-per-chip fees make use of an IP Core easy and simple.
Single Site license option – dedicated for small and middle sized companies, running their business at one location.
Multi Sites license option – dedicated for corpo-rate customers, running their business at several places. The licensed product can be used in selected company branches.
In all cases the number of IP Core instantiations within a project and the number of manufactured chips are unlimited. The license is royalty-per-chip free. There are no restrictions regarding the time of use. There are two formats of the delivered IP Core:

•       Verilog RTL synthesizable source code called HDL Source
•       FPGA EDIF/NGO/NGD/QXP/VQM called Netlist

Configuration

Several parameters of the D32PRO can be easily adjusted to requirements of a dedicated application and technology. The configuration of the core can be effortlessly done, by changing appropriate constants in the package file or using GUI. There is no need to change any parts of the HDL code.