DMAC - 10/100 Mb Media Access Controller

DMAC - 10/100 Mb Media Access Controller Description:

Overview

The DMAC is hardware implementation of media access control protocol defined by the IEEE standard. DMAC in cooperation with external PHY device enables network functionality in design. It is capable of transmitting and receiving Ethernet frames to and from the network. Half and full duplex modes are supported, as well 10 and 100 Mbit/s speed. The core is able to work with wide range of processors: 8, 16 and 32 bit data bus, with little or big endian byte order format. The DMAC provides static configuration of PHY IC. Design is technology independent and thus can be implemented in variety of process technologies. This core strictly conforms to IEEE 802.3 standard.

Features

■ Conforms to IEEE 802.3-2002 specification
■ Configurable width CPU interface with little or big endianess:
■ 8-bit
■ 16-bit
■ 32-bit
■ Simple interface allows easy connection to CPU
■ Narrow address bus (4 bits) with indirect I/O interface to the transmit and receive data dual port memories
■ Supports 10BASE-T and 100BASE-TX/FX IEEE 802.3 compliant MII PHYs
■ Media Independent Interface (MII) for connection to external 10/100 Mbps PHY transceivers
■ Supports full and half duplex operation at 10 Mbps or 100 Mbps
■ CRC-32 algorithm:
■ calculates the FCS nibble at a time
■ automatic FCS generation and checking
■ able to capture frames with CRC errors if required.
■ Dynamic PHY configuration by MII management interface
■ Early receive and transmit interrupts to increase data throughput
■ Programmable MAC address
■ Promiscuous mode support
■ Allows operation from a wide range of input bus clock frequencies
■ Fully synthesizable
■ Static synchronous design
■ Positive edge clocking
■ No internal tri-states
■ Lite design, small gate count and fast operation
■ Scan test ready

Benefits

■ Getting a silicon proven and technologically independent IP (VHDL and Verilog)
■ Rapid prototyping and time-to-market reduction
■ Design risk elimination
■ Development costs reduction
■ Full customization
■ Global sales network
■ Professional service
■ Fast responsive support

Deliverables

■ Source code:
■ VHDL Source Code or/and
■ VERILOG Source Code or/and
■ Encrypted, or plain text EDIF netlist
■ VHDL & VERILOG test bench environment
■ Active-HDL automatic simulation macros
■ ModelSim automatic simulation macros
■ Tests with reference responses
■ Technical documentation
■ Installation notes
■ HDL core specification
■ Datasheet
■ Synthesis scripts
■ Example application
■ Technical support

Tech Specs

Type - Soft Firm  

Availability - now

FPGA Technology:

Altera: Stratix II, Stratix GX, Stratix, HardCopy, FLEX 10K, Cyclone, APEX II, APEX 20KE, APEX 20KC,
Xilinx: Virtex-II Pro, Spartan-3,
Actel: SX-A, ProASICPLUS, Axcelerator,