D6802 - 8-bit Microprocessor

D6802 - 8-bit Microprocessor Description:

Overview

• two power saving modes: HALT, WAIT

• built-in real time hardware on chip debugger

• de-multiplexed Address/Data Bus to allow easy memory connection

The D6802 is a 8-bit MPU IP Core. The D6802 is synthesisable SOFT Microprocessor IP Core, fully compatible with the Motorola MC6802. It can be used as a direct replacement for the MC6802 Microprocessor.

Two software-controlled power-saving modes - WAIT and HALT, are available to conserve additional power. These modes make the D6802 IP Core especially attractive, for automotive and battery-driven applications.

The D6802 has built-in real time hardware on chip debugger - DoCDTM, which allows easy software debugging and validation.Our innovative IP Core is fully customizable - it is delivered in the exact configuration, to meet user's requirements. There is no need, to pay extra for not used features and wasted silicon. The D6802 includes fully automated testbench with complete set of tests, allowing easy package validation, at each stage of SoC design flow.

Each of the DCD's D68XX Cores, has a built-in support for DCD Hardware Debug System - DoCDTM. It is a real-time hardware debugger, which provides debugging capability of a whole System on Chip (SoC). Unlike other on-chip debuggers, the DoCDTM provides a non-intrusive debugging of running application. It can halt, run, step into or skip an instruction and read/write any contents of microprocessor. More details about DCD on Chip Debugger

Features

■ Cycle compatible with original implementation
■ Software compatible with industry standard MC6802
■ De-multiplexed Address/Data Bus to allow easy memory connection
■ Two power saving modes: HALT, WAIT
■ Fully synthesizable
■ Static synchronous design
■ No internal reset generator or gated clock
■ Scan test ready
■ One global system clock
■ Synchronous reset
■ All asynchronous input signals are synchronized before internal use

Deliverables

■ Source code:
■ VHDL Source Code or/and
■ VERILOG Source Code or/and
■ Encrypted, or plain text EDIF netlist
■ VHDL & VERILOG test bench environment
■ Active-HDL automatic simulation macros
■ ModelSim automatic simulation macros
■ Tests with reference responses
■ Technical documentation
■ Installation notes
■ HDL core specification
■ Datasheet
■ Synthesis scripts
■ Example application
■ Technical support
■ IP Core implementation support
■ 3 months maintenance
■ Delivery the IP Core updates, minor and major versions changes
■ Delivery the documentation updates
■ Phone & email support

Tech Specs

FPGA - All

Structured ASIC Target - All

Type - Soft  

Equivalent Part - MC6802

Compliant Standard - MC6802

Availability - now

FPGA Technology:

Altera: Stratix III, Stratix II GX, Stratix II, Stratix GX, Stratix, Cyclone II, Cyclone, APEX 20KE, APEX 20KC,
Xilinx: Virtex-II Pro, Virtex-5 FX, Virtex-4, Spartan-3E, Spartan-3A, Spartan-3,
Actel: IGLOO, Fusion,