DT8051 - Tiny Area High Performance Microcontroller

DT8051 - Tiny Area High Performance Microcontroller Description:

Overview

• Almost 10. times faster than standard 80C51 at the same frequency

• Ultimate low gate count

• Power Management Unit

The DT8051 is area optimized, tiny soft core, of a single-chip 8-bit embedded microcontroller, based on World's fastest and most popular DP8051 core, available since over 8 years. DT8051 soft core is 100% binary-compatible with the industry standard 8051 8-bit microcontroller. DT8051 has very low gate count architecture, giving 7 150 ASIC gates for complete system, including DoCD on-chip debugger. Dhrystone 2.1 benchmark program runs exactly 8.1 times faster, than the original 80C51 at the same frequency. The same C compiler was used for benchmarking of the core vs 80C51, with the same settings. DT8051 includes 2-wire DoCD on-chip debugger (TTAGTM), up to eight external interrupt sources, advanced Power Management Unit, Timers 0&1, I/O bit addressable Ports, full duplex UART and interface, for external SFR. DT8051 Core has built-in support for the 2-wire TTAGTM interface - DCD Hardware Debug System, called DoCDTM. This version of debugger is dedicated for applications, where number of external pins is limited.
The DT8051 is delivered with fully automated testbench and complete set of tests, allowing easy package validation, at each stage of SoC design flow.
Each of the DCD's 8051 Core, has built in support for the DCD Hardware Debug System, called DoCDTM. It is a real-time hardware debugger, which provides debugging capability of a whole System on Chip (SoC).

Unlike other on-chip debuggers, the DoCDTM provides non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, set breakpoints, watchpoints, read/write any contents of microcontroller, including all registers, internal and external program memories, all SFRs, including user defined peripherals. More details about DCD on Chip Debugger

Features

■ 100% software compatible with industry standard 8051
■ Very low gate count, area optimized architecture - 7 150 ASIC gates for complete system including DoCD on-chip debugger
■ 8.1 times faster than standard 80C51 at the same frequency
■ 7.63 VAX MIPS at 100 MHz
■ Up to 256 bytes of internal (on-chip) Data Memory
■ Up to 64 kB of internal (on-chip) or external (off-chip) Program Memory
■ Up to 64 kB of external (off-chip) Data Memory
■ De-multiplexed Address/Data bus to allow easy memory connection
■ Interface for additional Special Function Registers
■ DoCD - 2-wire debug unit
■ Power Management Unit
■ Interrupt Controller 11 interrupt sources
■ 8-bit I/O Port
■ Two 16-bit timer/counters
■ Full-duplex serial port
■ Fully synthesizable
■ Static synchronous design
■ Positive edge clocking and no internal tri-states
■ Scan test ready

Tech Specs

FPGA - Altera, Xilinx, Lattice

Type - Soft Firm  

Maturity - 8 years

Availability - now

TSMC - In Production : 130nm (CL013G)

UMC - In Production : 0.18µm

FPGA Technology:

Altera: Stratix IV , Stratix III, Stratix II, Cyclone III, Cyclone II,
Xilinx: Virtex-6, Virtex-5, Virtex-4, Spartan-6, Spartan-3E, Spartan-3A,
Actel: ProASICPLUS, ProASIC3L, ProASIC3 nano, ProASIC3, Fusion, Axcelerator,