DQ80251 - Revolutionary Quad-Pipelined Ultra High Performance Microcontroller

DQ80251 - Revolutionary Quad-Pipelined Ultra High Performance Microcontroller Description:

Overview

• Almost 60 times faster than the original 80C51

• Almost 5 times faster than 80C251 - at the same frequency

• Quad-Pipelined architecture

DQ80251 is a revolutionary Quad-Pipelined ultra high performance, speed optimized soft core, of a 16-bit/32-bit embedded microcontroller. The core has been designed with a special concern for performance to power consumption ratio. This ratio is extended by an advanced power management PMU unit. This product is built based on 11 years of DCD’s know-how, with triumphant 8051 architectures. DQ80251 soft core is 100% binary-compatible with the industry standard 16-bit 80C251 and 8-bit 80C51 microcontrollers. There are two working modes of the DQ80251: BINARY (where original 80C51 compiled code is executed) and SOURCE (native 80C251 mode, using all DQ80251 performance). DQ80251 has built-in, configurable DoCD-JTAG on chip debugger, supporting Keil DK251 and standalone DoCD debug software. Dhrystone 2.1 benchmark program runs 56.8 times faster than the original 80C51 and 4.81 times faster, than the original 80C251 at the same frequency. This performance can be also exploited to great advantage in low power applications, where the core can be clocked over fifty times slower, than the original implementation, for no performance penalty. Additionally, compiled code size for SOURCE mode is about 2 times smaller, comparing to identical standard 8051 code, since DQ80251 instructions are more effective.

The DQ80251 is delivered with fully automated testbench and complete set of tests, allowing easy package validation, at each stage of SoC design flow.

Each of the DCD's 80251 Core has built in support for the DCD Hardware Debug System, called DoCDTM. Unlike other on-chip debuggers, the DoCDTM provides non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller, including all registers, internal and external program memories and all SFRs, including user defined peripherals. More details about DCD on Chip Debugger

Features
 

■ 100% binary compatible with industry standard 80C251 implementing BINARY and SOURCE modes
■ Single clock period per most of instructions
■ Quad-Pipelined architecture enables to execute 56.8 times faster than the original 80C51 and 4.81 times faster than 80C251 at the same frequency
■ Up to 53.411 VAX MIPS at 100 MHz
■ Up to 8M bytes of Program Memory
■ Up to 32k bytes of internal (on-chip) Data Memory
■ Up to 8M bytes of external (off-chip) Data Memory
■ Up to 16 MB of total memory space for CODE and DATA
■ 64k bytes of extended stack space
■ User programmable Program Memory Wait States solution for wide range of memories speed
■ User programmable Extended Data Memory Wait States solution for wide range of memories speed
■ De-multiplexed Address/Data bus to allow easy connection to memory
■ Full Program Memory writes
■ Interface for additional Special Function Registers
■ Fully synthesizable
■ Static synchronous design
■ No internal tri-states
■ Scan test ready

FPGA - Altera, Xilinx, Lattice

Type - Soft Firm  

Maturity - 10 + 1 years

Availability - now

TSMC - Silicon Proven : 160nm (CL016LP)

FPGA Technology - Altera: Stratix IV , Stratix III, Cyclone III, Cyclone II,
                                Xilinx: Virtex-6, Virtex-5, Spartan-6, Spartan-3,