TAP Checker

TAP Checker Description:

The innovative tool suite enables the automatic generation of simulation vectors and test patterns for chip-level validation and verification of IEEE 1149.1 and IEEE 1149.6 compliant implementation. TAP Checker is based on modular platform architecture with a central database and individual licensed modules for data import, automatic test vector generation and data export. This structure enables a scalable tool suite that can also support new bus protocols without loosing backward compatibility. After importing the BSDL file a process which includes syntax, semantics, and consistency verification, the user has a multitude of parameterized options, providing the means to generate an optimised testbench.