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Tombstone defect

I've been struggling with this problem for a while. We ha... - Apr 24, 2003 by yukim  

yukim

#24288

Tombstone defect | 24 April, 2003

I've been struggling with this problem for a while.

We have two products: A, which is Ok and B, with tombstone defect (0603 & 0805 capacitor chips).

A & B have the same design: pad sizes, separation between pads, components orientation. Both have similar PCB size. At first, for both, we used 175 microns-thickness stencil, 1:1 aperture size and spike-to-peak type reflow profile. We use same components. Because of the defect, we changed the stencil thickness for B to 150 microns, reduced the aperture size to 1:0.9, changed the reflow profile with plateau preheat zone, etc., without possitive results. The chips are placed with HSP 4797. Also checked the vibration, feeders, nozzles.

The only difference is the PCB manufacturer. How could this affect? HAL finish seems ok.

Any suggestion will be appreciated. Thanks!

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#24291

Tombstone defect | 25 April, 2003

If what you say is accurate, two thing come to mind: * Pads on the board are incorrect for the tombstoning components. * Profile is different on the individual pads of tombstoning components.

We have heard of, but never seen, components [tants] that were not fabricated properly and moved on pads when epoxy cured during reflow.

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Jesus Fragoso

#24386

Tombstone defect | 1 May, 2003

Did you check board orientation into the reflow oven? (The Layout components are the same products A & B?)

Regards Jesus

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ken

#24399

Tombstone defect | 3 May, 2003

Did you check if the height of solder mask between two pads is higher than pads?

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Thomas

#24400

Tombstone defect | 4 May, 2003

Did u ever try a anti-tombstone solder paste to try to eliminate this problem ??

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gaoliangcheng

#24401

Tombstone defect | 5 May, 2003

Maybe you can check the thickness of the solder mask between the pads. If the highest of the solder mask exceed the pad,then the component which was placed will be unbalanced.

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Vijay

#24402

Tombstone defect | 5 May, 2003

Do not 'ON" the nitrogen during reflow. If the pad of the chip is bigger then reduce the pad width from out side. Reduce the ramp rate at any point of the profile below 1 deg c/sec.

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Vijay

#24403

Tombstone defect | 5 May, 2003

Do not 'ON" the nitrogen during reflow. If the pad of the chip is bigger then reduce the pad width from out side. Reduce the ramp rate at any point of the profile below 1 deg c/sec.

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k_h

#24404

Tombstone defect | 5 May, 2003

Stencil thickness = 175 microns? If my math is correct, 175u=0.175mil, and if that is english units then it is inches. I'm not understanding this correctly, please clarify for my sake please, are you saying the stencil thickness is 0.000175 inches thick?

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Grant

#24405

Tombstone defect | 5 May, 2003

Hi,

This is an interesting point. I use Koki paste from Japan, and it's wonderful, however what properties of solder paste would make it "anti tombstone" paste?

How does led free effect tomb-stoning? That would be interesting to know. We might go lead free, just because we don't want to come into contact with led based products in production.

Regards,

Grant

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RDR

#24407

Tombstone defect | 5 May, 2003

A micron is 1 millionth of a meter, this term is no longer used according to my dictionary. I would have to agree with the dictionary. Anyway, 175 microns is a little more than 6.8 mils.

Russ

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Kris

#24408

Tombstone defect | 5 May, 2003

Hi,

It is expected that lead-free will have reduced tomstoning. As it has a higher surface tension and does not wet as well as the tinlead paste it exibit lower tombstoning. Addiotnaly commercialy available lead-free alloys may not be true eutectic IE they will emal over a range of temperature. This will also benefit reduced tombstoning. Some of the anti tombstoning pastes might use this property

Thanks

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Grant

#24410

Tombstone defect | 6 May, 2003

Hi,

Ok, thanks for the reply, and this is really interesting. I wonder if there are any good articles about this to read somewhere.

Regards,

Grant

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yukim

#24411

Tombstone defect | 6 May, 2003

Hi, No, the layout is different, but both have chips located arallel and perpendicularly to the flow direction. And we do have defects in both orientation.

What about the PCB warpage? Sometimes we find warped PCBs. Could this affect?

Thanks, Yu.

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yukim

#24412

Tombstone defect | 6 May, 2003

The stencil thickness was about 7 mils and was changed to 6 mils.

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k_h

#24415

Tombstone defect | 6 May, 2003

Got it, thanks, I've always used english mils. Have you solved the problem yet yukim?

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yukim

#24424

Tombstone defect | 6 May, 2003

Yes, we did try: built a lot of 200 PCBs with Sn62Ag2 solder paste (we have been using Sn63) and it helped, but not eliminated the problem.

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Kris

#24427

Tombstone defect | 7 May, 2003

Hi

SnAg is a binary alloy and does not have the same effect as a ternary SnAgCu alloy as far the pasty range is concerned. But then paste only can do so much. The best way to do it is to have proper pad design, controlled placement and reflow.

I was wondering if for a unequal plating on the two terminations of the component would have any effect ?

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#24430

Tombstone defect | 7 May, 2003

Kris

The majority of our tombstoning in very small passive SMT is caused by imperfections in end-cap solderability protection plating.

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Grant

#24435

Tombstone defect | 7 May, 2003

Hi,

What brand passive components would you recomend for best quality of construction. We are never sure what's good and what's now, and what at some of the better brands.

Regards,

Grant

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#24437

Tombstone defect | 7 May, 2003

We like the passive components that the buyer gets to the stock room in time to meet the build plan. It's a plus if they take solder.

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T.Vick

#24521

Tombstone defect | 16 May, 2003

Yukim, Just another thought (way off the solder paste trail that you've been on so far)....Are the parts similar in thickness? The 4796 and 4797 HSP's have a closed loop function that compensates for variations in component thickness based on feedback from the line sensor, but not every customer chooses to use this. If you do not have this enabled, it is feasible that if you have them programmed to be the same thickness, you are not placing/seating these components into the paste the same (same height and pressure). If you have any questions about this please let me know.

Regards, Todd Vick, HSP Products-Universal Intruments

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#24522

Tombstone defect | 16 May, 2003

If the only difference between the two products is the board supplier I believe thats where I would start, we had a similar problem like this two months ago and it turned out to be a faulty (thin) HASL layer which did not meet our print tolerance. This allowed oxidation to developed which in turn caused a solderability problem which resulted in poor solder joints and tombstoning. Cross section a coulple of boards and check plating thicknesses. Also run a solderability test on the parts and the boards.

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Jon Fox

#24523

Tombstone defect | 16 May, 2003

The term is still valid and used everyday by those in the die placement and "micro"-electronics world. MILS is too hard to understand at that level. Its just easier to say 10 microns than 0.3937 mils.

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Thomas

#24525

Tombstone defect | 19 May, 2003

Hi Grant,

From what I know, it has something to do with the flux...Imagine if the temp difference of the flux is somehow slowed down..it would reduce the tendency of a stronger pull on one side of the pad...

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Zhenya

#24548

Tombstone defect | 21 May, 2003

Several things for your reference: 1. Starting with data collection: - Have you done a measle chart to illustrate the pattern of the defect? - Have you checked the corelation between shift/time and defects rate? - How about a pareto chart? - Do you use the same production line?

2. Analysis: - check you profile with at least one thermal couple on 0805/0603 - thermal mass variation between the two assmeblies thermal relief on your design: parts used, PCB - from you measle chart, you shall identify the top fall-out locations and rechcheck the profile there - do you use same solder paste? - check the way pad is defined: solder mask or copper - check the Cpk data of you PCB fab house

3. Experiment: - Suggest you to run experiments with bare boards and only those 0805 and 0603 to minimize variables - Suggest you to mix the bare boards and run down the line without order

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Franky

#24594

Tombstone defect | 26 May, 2003

Dear sir, I think so with every idea , everyone is correct , paste , pattern of pad design ,profiling or solder mask on PCB ,and one of the cause of tombstone that I found is alignment of machine placing and solder printing , from my experience many variation that disturb in our process of solder printing and placement machine , and this problem very difficult to solved it , sometime you are not ignor this problem also.

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#24643

Tombstone defect | 30 May, 2003

AIM has an article that includes anti-tombstoning solder paste information. It's called "Reducing The Tombstoning of Small Discrete Components" and is located at http://www.aimsolder.com/technical_articles.cfm#14

Or I can send a copy to anyone interested.

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#24644

Tombstone defect | 30 May, 2003

We also use microns to describe solder paste powder particle sizes.

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RDR

#24653

Tombstone defect | 30 May, 2003

Okay, Okay, I will convert to the metric system. I would still rather say 1 mm instead of 10 microns. As far as paste how about "really little" and "really really little" (type 3 and 4 respectively)

This term (micron)is good for people unlike me that don't have to convert everything into mils or such to get a handle on the size.

Russ

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yukim

#24690

Tombstone defect | 3 June, 2003

A question regarding the rampup slop: as we cannot make the preheat time long enough due to our reflow oven limits, a Loctite technician suggested we increase the rampup slope, between the initial point (25C) and 80C, to 4C/sec, as between these temperatures nothing happens to the flux activity. I am wondering if this could affect components. Thanks!

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yukim

#25619

Tombstone defect | 28 August, 2003

Hi, do you know how much the problem can be reduced by using anti-tombstoning solder paste?

I tried two different lots using same solder paste (containing Ag). With one we did not see any improvement and with the other one, a lot. So, I am not quite sure whether it is the solder paste or something else.

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V_Sa

#25867

Tombstone defect | 26 September, 2003

Yukim, I had experienced this problem with 0402 package. I resolved it 100% by reducing stencil thickness from 6 mils to 5 mils and changing the apetures from 1:1 to homebase.

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Neil D. M.

#28699

Tombstone defect | 20 May, 2004

Hi David,

Can you send me a copy of this article "Reducing The Tombstoning of Small Discrete Components". Thanks a lot.

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Jet

#29749

Tombstone defect | 30 July, 2004

Hi, Very interesting article on tombstone issue, i'm facing tombstone issue for 0805 IDC component, i've redesign the stencil aperture and change to lead free paste, the tombstone is reducing but not fully eliminated, however there is a problem i face on the rework process for 0805 IDC capacitor with using lead free paste, does anyone here hv a solution to share on the rework process?

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