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Voids in solder fillet

Takfire

#24168

Voids in solder fillet | 16 April, 2003

Recent cross-section analysis for a customer complaint revealed voiding in the solder fillet. In some cases, the remains of outgassing were also observed. During the failure analysis, we also observed failures where the solder fillet wicked on the top surface of the chip capacitor, appearing as if too much solder was applied. I am trying to resolve the issue with the customer by recommending evaluation of their reflow temperatures and respective profiles.

Are there other causes for voiding (i.e.: excessive stencil height, solder paste quality)?

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RDR

#24169

Voids in solder fillet | 16 April, 2003

What was the original complaint? when you say solder wicked onto top of capacitor do you mean it was dewetted from the board and only on the cap? What type of device showed voiding? how bad was it 20%,50%? I have found that the paste type seems to be a major contributor to voids but, the profile can also reduce/increase voiding. I know I answered no question yet but would like some more information.

Russ

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Takfire

#24170

Voids in solder fillet | 16 April, 2003

Thanks Russ! The origianal complaint from the customer was in regards to what appeared as "bumpy" appearance and "holes" in the solder fillet. This problem was originally presented as an appearance issue only. Further investigation by our DPA lab revealed the voids. No, the fillet was not dewetted from the solder land. Instead, the paste wetted to the top of the capacitor and remained in contact with the PCB. It almost appears as if too much solder paste was applied during the stencil process and wicked on top of the capacitor during the liquidous state. The voiding in the solder fillet was present on both capacitors and resistors within the module. The level of voiding was not evaluated through X-ray, acoustic imaging or other non-destructive techniques. The voids were observed through cross-section analysis and are loosely estmated to be betwen 5 and 20 percent of the solder fillet. It's tough to evaluate from cross-section analysis alone. Thanks again for your assistance.

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RDR

#24172

Voids in solder fillet | 16 April, 2003

Thanks for the info, Here is a couple more questions (and you thought you were done) What size are these caps /res? how thick is your stencil? what type of oven are you using? what is the finish of the board?

Anyway, it seems like (from a distance)that you could cut back on the paste application. You want to try and achieve a solder fillet that extends somewhere around 1/3 to 2/3 of component height. What could possibly be happening (i am thinking out loud here)is due to the large amount of paste applied the soak temp and duration may not be high and long enough to drive out all of the volatiles in the paste. Or it could possible be the opposite and you are drying out the flux before reflow. I would recommend verifying the profile to your paste mfg. recommended, ensure that you are using good paste (date code, non-separated, etc). you can expect to see some voiding in solder joints that does not necessarily mean your process is bad but if they affect the appearance and leave holes in the joints then I would think that something is not quite right. hopefully some of the other fine folk here on the SMTNET can provide some additional feedback

Russ

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#24180

Voids in solder fillet | 17 April, 2003

While Russ is correct that a little voiding is OK, your level of voiding [customer complains that the solder surface looks bumpy] doesn't give us the ol' warm and fuzzy about their process control.

For background: * Search the fine SMTnet Archives. There's a fair amount of discussion on voiding there. * Get a hold of some of the papers published by Dr. Lee at Indium Corp. He has conducted a number of investigations concerning solder joint voiding.

Things to think about are: * Paste suppliers matter, but if this is not a wide spread problem, then it's probably something else. * Higher volume of paste increases voids. * Minimizing time between print and reflow is critical. * Soak temperature should be within solder paste supplier recommendations. * Soak for 2.5 min or greater. If you soak this long, you soak temperature has little impact.

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Takfire

#24183

Voids in solder fillet | 17 April, 2003

Russ, The caps are 0603 case size. I am not sure about the manufacturing details, as I work for the capacitor supplier. The manufacturing details are unclear at the moment, as the customer (South of the border) has not released such detailed information. I also suspect that variation in the amount of paste stenciled on the PCB is one of the contributors to the problem. We concur with the solder fillet height and have suggested the height approach 50% of the componenet height. We have also recommended that the customer test the reflow temperature profile in regards to the ramp temperature, peak temperature and soak durations. Unfortunately, the customer is convinced that this is a capacitor quality issue with out thoroughly investigating their process.

I am planning to visit the customer next week with the solder paste manufacturer. Perhaps the solder paste manufacturer will shed additional light to the profile errors that are present.

Thanks for your great input!

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Takfire

#24184

Voids in solder fillet | 17 April, 2003

Thanks Dave! What level of voiding is acceptable? Would you please let me know if there is an EIA or other industry standard detailing solder joint quality? I will begin researching the background information you provided. Thanks again for your kindess and response.

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#24185

Voids in solder fillet | 17 April, 2003

A-610 talks to acceptable voiding.

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#24186

Voids in solder fillet | 17 April, 2003

Takfire

Questions are: * Why does your customer think the capacitor is the issue? [What are we thinking? Of course the capacitor is causing this voiding problem. What else could it be?] * What are the type, construction, end-cap material and plating, etc of the capacitor? * What kind of solderability tests to you run for process control?

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#24188

Voids in solder fillet | 17 April, 2003

This is not quite what you're asking, but for BGA acceptance: * NASA allows: �Terminations that exhibit less than 10% voiding in the ball-to-board interface are acceptable.� [Or words to that effect] * According to IPC-7095, Void in ball: ||Class1|| Accept|| Reject ||||60% of ball diameter|| >60% ||||36% of ball area|| >36% ||Class2|| Accept|| Reject ||||45% of ball diameter|| >45% ||||20.25% of ball area|| >20.25% ||Class3|| Accept|| Reject ||||30% of ball diameter|| >30% ||||09% of ball area|| >09%

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#24189

Voids in solder fillet | 17 April, 2003

Background: * Bulwith, Ronald A., �Failure Analysis of Solder Joints�, �Insulation/Circuits� magazine, February 1978 * Banks, Donald R., et al., �The Effects of Solder Joint Voiding on Plastic Ball Grid Array Reliability�, Proceedings of the Technical Program - Surface Mount International, September 10-12, 1996 * http://www.smtinfocus.com/smt_failures/smt_failure_voiding.html

Voids in solder connection fishbone: ||Material ||||Part solderability ||||Board solderability ||||Solder paste ||||||Flux activity ||||||Age ||||||Storage ||||||Air bubbles ||||||Type solder ball ||Machine ||||Reflow oven ||||||Preheat recipe ||||||Peak temperature recipe ||||||Time in oven ||||Paste print ||||||Squeegee type ||||||Stencil alignment ||||||Stencil design ||Personnel ||||Operator ||||||Training ||||||Experience ||||Inspector ||||||Training ||||||Experience ||||||Inspection criteria ||Methodology ||||Paste application ||||Printer set-up ||||Printer operation ||Management ||||Attitude / Support ||||Understanding

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Takfire

#24190

Voids in solder fillet | 17 April, 2003

Dave, I am not exactly sure what is driving them to believe that this is a capacitor issue. It is unfortunate, that this belief has slowed their activity in further understanding their manufacturing process.

The caps are BME (Base Metal Electrode), multilayer ceramic chip capacitors. The end cap material is constructed of Cu with Ni and Sn plating. Solderability is evaluated by performing wetting balance and single piece dipping for solder coverage and to evaluate the resistance to solder heat (sample basis). XRF is also performed on a sample basis to ensure the Ni and Sn plating thicknesses are within specifications.

At first, I was afraid that the parts were contaminated or had too thick of a Sn plating layer. Both cases were not true. The parts were found to be typical of our product profile.

I firmly believe that we are being called on the carpet to resolve their issue. That is what prompted me to post on this great forum. I need as much information as possible to play devil's advocate to the customer in order to help them redirect the focus to further evaluate their process.

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Takfire

#24191

Voids in solder fillet | 17 April, 2003

Dave,

I truly appreciate your efforts in providing information. Excellent input with the fishbone data. I will put together a presentation later tonight. I hope to return the favor in the future in regards to MLCC manufacturing or application. Kind regards

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#24192

Voids in solder fillet | 17 April, 2003

We undoubtedly will take you up on that offer. Please email contact information.

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#24193

Voids in solder fillet | 17 April, 2003

Q1: Industry standard detailing solder joint quality? A1: ANSI/J-STD-001 - Requirements For Soldered Electrical & Electronis Assemblies is the mutha of industry standard detailing solder joint quality.

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