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BGA voids

Eric Brown

#22987

BGA voids | 13 January, 2003

Does anyone know of documentation that specifies whether or not voids in BGA solder joints hurt or help performance?

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Jon Fox

#22990

BGA voids | 13 January, 2003

I was looking for some good documentation that could nail down some pros/cons of voids, but haven't found any. The biggest issue is if you are going to temp cycle the chips/PCB after assembly. Depending on the cycle, the situation of the test, it could get worse. Remember that voids will effect the following: direct current resistance, switching noise, signal delay, capacitance, and inductance. Values will decrease at extremely lower temperatures as the SnPb (assuming you're not using PB free) constricts slightly and the opposite at higher temperatures. I know that this isn't the hard evidence that you are looking for, but just the physics that is going on behind the scenes in your BGA joint. Also, if you are not using a Pb based solder that the Pb free mixes have their own special electrical pros/cons to take in account for.

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#22991

BGA voids | 13 January, 2003

Here ya go: * Get some of the papers published by Dr. Lee at Indium Corp. He has conducted a number of investigations concerning solder joint voiding and BGA components. * Read EP&P 10/98 says something like: ** Number of small and large voids correlate. ** Reflow time (temperature) is (are) very significant in void formation. Soak time is not a factor. *** Increasing reflow temperature increases voiding. Temperature influences void formation 8.4X times greater than reflow time *** Increasing reflow time decreases voiding ** Small voids near the base (top) of the ball, increase reflow time (60 -> 100 sec) and decrease reflow temp to 205C. * Understand that voids are primarily process indicators. There is experimental evidence that voids retard crack propagation locally around the void on a temporary basis. There is no standard, IPC or otherwise, on voids -- nor should there be. See also J-STD-013, Implementation of Ball Grid Array and Other High Density Technology. * April 2000 SMT Magazine, regarding the benefits of a Ramp-to-Spike profile. According to the author, voiding generally results from one of three causes; insufficient peak temperature, insufficient time at temperature, or excessive temperature in the ramp zone. * Some BGA come with voids already in the solder balls--you may want to check for this. The problem with this scenario is reduced solder volume. If your processes create the voids, it is only a problem if a shear test shows a failure mode through the solder balls with voids rather than near the interfaces or pads. * Find something titled, maybe "Voids in BGA [Intel] Device Voids in the BGA ball"

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TinSon

#23032

BGA voids | 15 January, 2003

How about section 12.2.12 of IPC-A-610C? It doesn't include detailed description of root cause/effect but acceptance criteria.

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JohnW

#23034

BGA voids | 16 January, 2003

The IPC 610 actally conflict's with 7095 which give's a better indication of what's acceptable. I believe that IPC are reviewing both. Motorola did a bunch of work before basically showing that void's aren't that bad up to a certain size, I think probably if it was 60 - 70% of the ball area then you have a problem. the problem is that no one has actually done definative work that voids are good / bad / indifferent. It probably also matter's about what frequency the devices work at in term's of resonance cavities and so forth but that I think would be few and far between. Also I'm sure we did a thread on this a while back so it would be worth having a search. Plus I have a sneaky feeling that you'll get more info out of this year's APEX.

JohnW

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