was going thru the IPC-A-610C Standards, and noted BGA voids stands somewhere between 10%-25% voids permissible in the solder "ball" bump, after reflow process.
Was wondering, hypothetical case study, is there any specification for voids in LGA (land grid array) solder joints? both for :
1) the solder fillet contact beneath the LGA pads and PCB pads?
2) the solder fillet forming the external side wall solder fillet joint (ie. solder slope contacting LGA side wall)?
3a) If there is such a voids specs for LGA, where and what Standards documentation is this specs written?
3b) If there is no established documentation explict for voids in LGA solder fillet joints, is there any Standards that makes some referrence that can assist future establishment of such specs?
Appreciate all feedback, comments and opinions. Thanks in advance, mates. Cheers!
a) went thru the index page of IPC-A-610C, it does refer to section 12.2.12, 6.5.4, 12.4.8 to establish possible component solder joint "external visual" limitations.
b) such limitations manifest as displayed symptoms of blow-hole/pin-holes. Voids (in my opinion) are visually visible only by virtue of (NDT)X-RAY photo/image or destructive shear test sampling.
c) the listed limitations mentioned, do not specify the dimensional tolerances for voids (eg. like 10% of surface area? or so-&-so degree of mils/mm measurement value)? this is our primary concern to qualify voids specifications?