Printed Circuit Board Assembly & PCB Design SMT Electronics Assembly Manufacturing Forum

Printed Circuit Board Assembly & PCB Design Forum

SMT electronics assembly manufacturing forum.

solder crack



solder crack | 30 June, 2002

the SOIC encounter solder crack after reliability test, the common process is: SMT---manual soldering---IPT(in process test)---potting---T/C(thermal cycling,only add current and voltage)---B/T and F/T (burn in and functional test). the condition is 2 cycle between -40 and 100 celuis, 0.5hrs/cycle. so when we produce many boards and this issue is happening, how to sort these PCBA? thanks

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solder crack | 1 July, 2002

Possible cause can be design related- if the solder land is too small. Check w/ IPC SM-782 Solder Land Design Guide Another is board finish. I have seen problems like this with Gold finished PWBs- which creates a more brittle solder joint.Another possibility is profile. Run the profile on the SOIC joints and see what you get compared to other points on the board. What alloy is the lead? I have seen problems with leads made from aluminum alloys- mostly on Toshiba TSOP components. Be sure the device is designed to go -40 to +100 and at the rate-of-change you cycle it at.

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solder crack | 1 July, 2002

Comments [questions] are: * It�s strange that an uggie ol� SOIC, 50 pitch, BIG honkin� solder pad, kinda thang is failing. Sumpin aint kosher, yano? * Where is the failure occurring [ie, lead to pad, pad to board, etc]? Talk about the breadth and distribution of the problem. * We have found that the curing of potting can damage solder connections. What compound are you using? What is your cure recipe? * Your accelerated environmental testing is aggressive, regardless of the product end-use environment. Consider reviewing the need for cycling below 0�C. Understand why you�re not using a dwell of maybe 15 minutes, depending on the assembly [just enough time to get it to temperature]. You could increase your ramp to <20�C/min to compensate, somewhat, for the time lost to dwell. What is the product end-use environment? [Well, maybe the thinking on the �slow ramp / no dwell� was that with a slow ramp, the dwell wasn�t needed. Could be.] Finally, does this temperature measurement include the effect of voltage and current on the assembly? Or is this �box temperature�? * Sometimes cracking like this can be tracked back to board design. If this is limited is scope, talk about pad dimension, spacing, and shape. * How are sure the IPT (in process test) is capable of detecting the problem?

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