Printed Circuit Board Assembly & PCB Design SMT Electronics Assembly Manufacturing Forum

Printed Circuit Board Assembly & PCB Design Forum

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Geometric Dimensioning and Tolerancing

Earl Moon


Geometric Dimensioning and Tolerancing | 6 June, 1998

GEOMETRIC DIMENSIONING AND TOLERANCING (GDT) Using and applying GDT to printed circuitry and assemblies is very much like applying it to any other design for manufacturing (DFM) or design for assembly (DFA) requirement using concurrent engineering (CE) principles and methods. This means, the designer must be able to convey product requirements, as drawings with clearly defined dimensions and tolerances, to those making product. It also implies the designer understands the manufacturing process into which the design will be introduced so DFM and DFA processes are unidirectional. At first, GDT would seem better suited to applications concerning machined or formed metal products, as examples. They can be "gaged" to the extent the part is assured to fit as specified. Upon second consideration, printed circuit boards and assemblies share the same principle and can benefit equally from GDT. This is especially so considering programmable, automated design and manufacturing operations sharing (or should and will eventually) a common design to manufacturing language and input capability as CAD/CAM and EDT. ANSI Y14M clearly indicates, for components requiring assembly, there currently is not other technique capable of accurately organizing the necessary thought processes required in the DFM/DFA/CE system. It ensures all cognizant CE people address pertinent points as the product cycle proceeds. ANSI Y14M provides a list of rules that are pertinent to CE. The are abbreviated as follows: 1) Each dimension shall have a tolerance 2) Dimensions for size, form, and the location of features shall be complete so there is full understanding of each feature's characteristics. 3) Each product's necessary dimensions shall be shown. 4) Dimensions shall be selected and arranged to suit the part's function and mating relationship. 5) Each dimension shall be clearly defined to not allow more than one interpretation. 6) Each drawing shall define parts without specifying a manufacturing process or method. Each item, and all, require discussion between all individuals involved in the DFM/DFA process. This is true, as more scrutiny is applied to the list, from design through test and concept to customer satisfaction. I simply wanted to address this issue as vital especially considering the pace at which we all travel while attempting better quality. To assure it, we must apply tools to better manage processes with a concurrence between all those involved. Somehow, we in the printed circuit business seem to have fallen back a bit on this subject as this often is indicated by some of the questions repeated in this forum. Thanks, Earl Moon

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Re: Geometric Dimensioning and Tolerancing | 6 June, 1998

Earl, As always, I am interested in what you have to say, but I am still a little vague on your application of ANSI Y14.5 as it relates to the manufacturability of an assembled printed circuit board. Are you implying that component placement coordinates will be dimensioned from a common datum. Please clarify. Thanks, The Boys at EFData

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Earl Moon


Re: Geometric Dimensioning and Tolerancing | 7 June, 1998

| Earl, | As always, I am interested in what you have to say, but I am still a little vague on your application of ANSI Y14.5 as it relates to the manufacturability of an assembled printed circuit board. Are you implying that component placement coordinates will be dimensioned from a common datum. Please clarify. | Thanks, | The Boys at EFData Well EF Data boys, and girls I hope, what keeps you up all hours on a Saturday night? Could it be you�ve nothing better to do, or have you no other life? We all have our ways of enjoying and being punished. I am not trying to imply anything with my simple posting, concerning a complex issue (that shouldn�t be), in this forum. Simply, I seek to illicit responses from folks as you and others concerned with process management improvement and the quality affected and effected by it. We all seek designs capable of being produced on time, the first time, every time, at the lowest cost with the highest customer satisfaction. All fine words that are rapidly becoming reality. However, some of us have more distance to travel than others before rhetoric garners real meaning. I am one. What I�m really getting at is concurrent engineering (CE) and the glue that binds it all together. This glue is the philosophy and reality ANSI Y14.5M, and GDT, provides. When the five fundamental concepts of the standard are applied, reality is possible as we seek to design product capable of not only being made at all - in the first place, but being made right the first time with minimal changes later. So often, in this forum, others, and in our jobs, we see clearly with hindsight. Certainly, this is part of the learning process. However, we all seek to apply lessons to continuously improve quality through more effective process management starting at the design level - where we all must clearly see all the affects processes are certain to have on decisions we make at that level. Data reference frames are but one of the five elements expressed so well in ANSI Y14.5M. The others compliment the first and provide the ability to focus all DFM/DFA/CE team members on what it takes to make manufacturable, acceptable product. More specifically, the printed circuit fabrication and assembly business is just beginning to realize the benefits of CE, based on the ANSI standard, and GDT. This is self admitted by some (as evidenced by IPC�s GDT training efforts meeting some resistance) no matter how talk is bantered around telling us all how much it is understood and how all knowing suppliers apply DFM principles and methods. The truth is we need to apply more specific methods to ensure many of the questions asked in this and other forums are put to rest, or less often repeated, so we can build higher quality product the first time. DFM and DFA are meaningless terms without CE and its glue. Some questions are obvious from those concerning electronic data transfer (EDT) and how CAD information is not always translated accurately into useful CAM information. Also, translating English dimensions and tolerances into Metric often provides problems. Mislocated or missing holes and pads, wrong hole or pad sizes, or poorly dimensioned fabs, not using a single datum, often bring complaints. Stencil opening sizes, tolerances, locations, and material thickness often cause problems. And on it goes as these are relatively simple issues (not problems) that must be resolved at the design level not withstanding those concerning other physical elements required to make PCB fabrication and assembly more effective and efficient. CE, cemented together with ANSI Y14.5M requirements, makes more sense than some of the ways things are being done currently. Please note this is not a complaint. It simply is a point of discussion I feel needs much more attention to minimize some of the issues concerning us all on our jobs and in this forum. Thanks again, Earl Moon

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