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solder thief guidelines - Aug 03, 1998 by

Re: solder thief guidelines - Aug 04, 1998 by

Re: solder thief guidelines - Aug 04, 1998 by

Re: solder thief guidelines - Aug 04, 1998 by

Ted Nicholas

#14800

solder thief guidelines | 3 August, 1998

I am looking for some design guidelines (length, width, spacing) for solder thieves which are placed behind trailing pins of wave soldered SOICs. I'd appreciate it if some one could direct me to the appropropriate reference. Also, has any one performed any experiments to determine the optimal solder thief design? Thanks for the help. Ted

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Chrys

#14802

Re: solder thief guidelines | 4 August, 1998

| | I am looking for some design guidelines (length, width, spacing) for solder thieves which are placed behind trailing pins of wave soldered SOICs. I'd appreciate it if some one could direct me to the appropropriate reference. | Also, has any one performed any experiments to determine the optimal solder thief design? | Thanks for the help. | Ted Ted, Not very scientific, but I always use a footprint that looks just like the SOIC with two extra pads trailing behind it. It's probably not optimal, but it's a no-brainer for SOIC's and it works fine. Chrys

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Steve Gregory

#14803

Re: solder thief guidelines | 4 August, 1998

| | | | I am looking for some design guidelines (length, width, spacing) for solder thieves which are placed behind trailing pins of wave soldered SOICs. I'd appreciate it if some one could direct me to the appropropriate reference. | | Also, has any one performed any experiments to determine the optimal solder thief design? | | Thanks for the help. | | Ted | Ted, | Not very scientific, but I always use a footprint that looks just like the SOIC with two extra pads trailing behind it. It's probably not optimal, but it's a no-brainer for SOIC's and it works fine. | Chrys Hi Ted! My input isn't very scientific either, just some experience working in contract manufacturing seeing quite a few different designs out on the production floor. Chris is right, pretty much the same size pad as the what's in the footprint will work...although I've seen pads that are slightly larger work even better. With the same sized pads occasionally, and ONLY occassionally, I'll see one or two bridges...nothing to really speak of. With the larger thieving pads I've never seen a bridge on a 50-mil pitch SOIC. One other thing about SOIC pads that you can do to reduce the bridging on the bottom, is to make the pads .020" wide, it's a little narrower than what IPC calls out, but it reduces the chance of shorts when wave soldering. Also, if you're only gonna put the pads on the trailing edge of the SOIC, be absolutely sure of what that direction is gonna be, it would suck a little bit to lay the pads out for one direction and have to run the board in the other... -Steve Gregory-

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Bob Willis

#14801

Re: solder thief guidelines | 4 August, 1998

The design rules for solder thiefs are that the extra pads must be bigger than the proceeding pads to be worth while as a minimum guide the pad is 3x the size of the proceeding pad so if the pad is 0.030" the thief would be 0.090" wide. As steve has said when you reduce pad width you decrease shorting. Standard pad width with IPC and others is 0.026-0.028" which is too wide. A 0.020" wide pad will make shorting less common but still add the thief. If you need any other information one of my Nepcon West 1999 Workshops is Wave Soldering Surface Mount with Zero Defects |

| I am looking for some design guidelines (length, width, spacing) for solder thieves which are placed behind trailing pins of wave soldered SOICs. I'd appreciate it if some one could direct me to the appropropriate reference. | Also, has any one performed any experiments to determine the optimal solder thief design? | Thanks for the help. | Ted

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