Printed Circuit Board Assembly & PCB Design SMT Electronics Assembly Manufacturing Forum

Printed Circuit Board Assembly & PCB Design Forum

SMT electronics assembly manufacturing forum.


Bill Boles

#14478

Help!: PBC Trace Failures at SMT pads! | 31 August, 1998

We have an unusual problem here and I'm reaching for more input if anyone can help??? We are an OEM manufacturer of PCA's. After a history of consistent quality designs, we have one small memory SIMM that is causing major headaches for us and our PCB mfgr. (a 1st class and reputable board-house). The PCB is designed to 6/5 design rules and is delivered to us after complete electrical testing. In post-production testing, we are finding 20-50% board failures in two separate production runs. Sometimes the boards work for 10-20 hrs. before failure. The affected traces are always found to be broken/open at the "heel" of a SMT pad where the trace connects to the pad. The PCB mfgr. has a 1 mil solder mask clearance that exposes the trace where it fails. The boards go through the HASL process and have gold-plated fingers for the SIM socket. It was suggested that the gold plating process could be affecting us somehow...is this possible? This design doesn't have teardrops, but has prompted us to use teardrops on every design since...(maybe this will help??) Why are the traces only "breaking" at the SMT pads??? I'd appreciate any insight. Bill Boles billb@memx.com

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davef

#14479

Re: Help!: PBC Trace Failures at SMT pads! | 3 September, 1998

| We have an unusual problem here and I'm reaching for more input if anyone can help??? We are an OEM manufacturer of PCA's. After a history of consistent quality designs, we have one small memory SIMM that is causing major headaches for us and our PCB mfgr. (a 1st class and reputable board-house). | The PCB is designed to 6/5 design rules and is delivered to us after complete electrical testing. In post-production testing, we are finding 20-50% board failures in two separate production runs. Sometimes the boards work for 10-20 hrs. before failure. The affected traces are always found to be broken/open at the "heel" of a SMT pad where the trace connects to the pad. The PCB mfgr. has a 1 mil solder mask clearance that exposes the trace where it fails. | The boards go through the HASL process and have gold-plated fingers for the SIM socket. It was suggested that the gold plating process could be affecting us somehow...is this possible? This design doesn't have teardrops, but has prompted us to use teardrops on every design since...(maybe this will help??) Why are the traces only "breaking" at the SMT pads??? | I'd appreciate any insight. | Bill Boles | billb@memx.com Bill: Very curious. Thoughts are: 1 What do the breaks look like? Could some of the connections be fuses? 2 What is your supplier's process for doing selective gold plating? 3 How thick are the platings? 4 When did they do the gold plating, relative to the HASL? 5 Was the board totally gold plated and then stripped for the before adding the HASL? 6 Have you (or someone) done any sections on the trace connection points to the pads on failed and not failed boards? You might throw this up for grabs on IPC Technet (http://www.ipc.org). There is a lot of knowledge about fab and assembly over there. Good luck Dave F

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