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Wirat Sriamonkitkul

#12926

Void in solder bump | 14 January, 1999

I saw the problem of void in solder bump or in lead less component or some BGA. But I didn't have standard specification of that void is accept or reject? Do any body have the better idea or suggestion of the criteria ?

Thank you, Wirat S. / Jan 15, 99

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Jason Hall

#12927

Re: Void in solder bump | 15 January, 1999

| I saw the problem of void in solder bump or in lead less component or some BGA. But I didn't have standard specification of that void is accept or reject? Do any body have the better idea or suggestion of the criteria ? | | Thank you, | Wirat S. / Jan 15, 99 | The information you are looking for is specific to each customer and sometimes each product. Very few use the same standard, and what they do go by changes daily. Your best bet is to get in touch with your customers and have them keep you in the loop when the decisions are made.

Thank You,

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Jim Nunns

#12928

Re: Void in solder bump | 15 January, 1999

Our spec on voids is 30% ball diameter in the center. On the component to ball and pad to ball interface, we use 25%. To determine this spec, we asked around. I don't know of any studies that have been done to verify if this is OK

Regards Jim

| I saw the problem of void in solder bump or in lead less component or some BGA. But I didn't have standard specification of that void is accept or reject? Do any body have the better idea or suggestion of the criteria ? | | Thank you, | Wirat S. / Jan 15, 99 |

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Earl Moon

#12929

Re: Void in solder bump | 15 January, 1999

| I saw the problem of void in solder bump or in lead less component or some BGA. But I didn't have standard specification of that void is accept or reject? Do any body have the better idea or suggestion of the criteria ? | | Thank you, | Wirat S. / Jan 15, 99 | Studies are ongoing. No concrete decisions have been made for BGA as yet, but the 20% range (with caveats) is becoming more likely. I know this doesn't address your question directly, but it is a starting point until you, or someone else (see below) does the failure analysis testing.

The following is an answer (provided by a very knowledgeable lady) to a similar question posed on IPC's TechNet:

Date: Fri, 8 Jan 1999 08:42:48 -0500 Reply-To: "TechNet E-Mail Forum." , Bev Christian Sender: TechNet From: Bev Christian Subject: Re: SOIC solder joint integrity X-To: Guenter Grossmann Content-Type: text/plain

Guenter, I'm not quite sure I know what you mean when you say "There is no test for the mechanical properties of a solder joint of a component." I have in my hot little hands (well actually cold big hands, its -19C here this morning) a copy of IPC-SM-785 "Guidelines for Accelerated Reliability Testing of Surface Mount Attachments". Werner and friends have put this together and surely this type of testing gives an indication of the sum total of the mechanical properties of solder joints, doesn't it? There are a few other "tests" that come to my mind as well. They include: plain old visual inspection (is there a good heel fillet?), solder pot analysis (if you have concerns about the PTH joints) and finally pull and shear testing. Now before the reliability gurus start lashing me with flex cables (worse if components are on them!) let me say that this is a test of the "now" strength of the joints and is not necessarily a measure of the long term reliability of a solder joint. It sure gives you a measure of possible infant mortality failures due to solder joint weakness, though.

Bev Christian Nortel Belleville, Ontario CANADA

Please note reference to the IPC document and to the name Werner. Visit the IPC forum and ask for the document and ask Werner to comment on your question.

Earl Moon

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Terry Burnette

#12930

Re: Void in solder bump | 15 January, 1999

| I saw the problem of void in solder bump or in lead less component or some BGA. But I didn't have standard specification of that void is accept or reject? Do any body have the better idea or suggestion of the criteria ? | | Thank you, | Wirat S. / Jan 15, 99

I am sending you a copy of a paper we presented at the Sept. 1996, Surface Mount International Conference. The paper is titled "The Effects of Solder Joint Voiding on Plastic Ball Grid Array Reliability". We performed a solder joint reliability study on BGA's with three levels of solder voids; no voids, nominal, and high voids. The PBGA's which had the high volume of voids, had improved reliability over PBGA's which had little to no voids. Solder joints with voids which measured 24% of the pad geometry, survived 16% longer than those solder joints which had no voids. Analysis, after temperature cycling indicated that the reliability improvement occurs because once a crack propagates to a void, it must re-initiate,in the opposite side of the void, to proceed further. This re-initiation causes a time delay in the total time it takes a solder joint to fully fracture. As a follow up to the 1996 study, we are presently temperature cycling (-40�C/+125�C) PBGA's which have void structures greater than 30% of the pad geometry. As of today, we have 1,630 cycles without a single solder joint failure. We continually monitor the solder joints under test, and will be able to tell when the first joint fails. Once temperature cycling, and analysis is complete, we plan on publishing the results.

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Jason Hall

#12931

Re: Void in solder bump | 15 January, 1999

| Our spec on voids is 30% ball diameter in the center. On the component to ball and pad to ball interface, we use 25%. To determine this spec, we asked around. I don't know of any studies that have been done to verify if this is OK | | Regards | Jim | | | I saw the problem of void in solder bump or in lead less component or some BGA. But I didn't have standard specification of that void is accept or reject? Do any body have the better idea or suggestion of the criteria ? | | | | Thank you, | | Wirat S. / Jan 15, 99 | | | For those of you that want specific guidelines please send me e-mail containing the customer and I will get back to you on the exact void allowance. I would post it here but there is not enough room! If this does not work the customer would be more than greatful to give you dimension acceptabilities for each product you build.

Hope I can help | |

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Wirat S.

#12932

Re: Void in solder bump | 16 January, 1999

| | Our spec on voids is 30% ball diameter in the center. On the component to ball and pad to ball interface, we use 25%. To determine this spec, we asked around. I don't know of any studies that have been done to verify if this is OK | | | | Regards | | Jim | | | | | I saw the problem of void in solder bump on in lead less component or some BGA. But I didn't have standard specification of that void is accept or reject? Do any body have the better idea or suggestion of the criteria ? | | | | | | Thank you, | | | Wirat S. / Jan 15, 99 | | | | | For those of you that want specific guidelines please send me e-mail containing the customer and I will get back to you on the exact void allowance. I would post it here but there is not enough room! If this does not work the customer would be more than greatful to give you dimension acceptabilities for each product you build. | | Hope I can help | | | | | Dear Sir,

Thank you for every feedback, I think in the range of 20% - 25% of void in solder are acceptable, it depend to our products application and component packaging type. Right now, i saw problem of lead less SMD size very close to Tant-C, saw a little small void around the solder join. But other SMD component in the same assembly was good, no viod.

I'm very interested to see the result of study with ESS. It may give us a guide line to revised our specification again. I am looking for the result of ESS study.

Since the specification of void in solder is not the concrete yet. Can I change a question ? Instead of specification of void solder to what is the root cause and how to eliminate or minimize the problem in our assembly process ?

I assembly PCBA FR4 with PBGA or Lead less component, with clean solder paste (water soluble paste) type 2, PBGA was in the second reflow. Reflow with hot oven. I used to baking PCB FAB 1-2 Hrs at 120 C +/- 5 degree C and PBGA baking at 125 C =/- 5 degree C. But x-ray after second reflow still saw a little void in solder. Why did it coming from? - PCB FR4 Multilayer was out gasing during reflow? - Moisture in the component or PCB? - Incomplete melting of solder paste? or flux residue? - Wrong reflow profile? PBGA require special profile? Appreciate every input from your experience.

Best Regards, Wirat S. / Jan 16, 99 email : wiratsr@gssthai.com

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Kenneth Hedman

#12933

Re: Void in solder bump | 6 August, 1999

| | I saw the problem of void in solder bump or in lead less component or some BGA. But I didn't have standard specification of that void is accept or reject? Do any body have the better idea or suggestion of the criteria ? | | | | Thank you, | | Wirat S. / Jan 15, 99 | | I am sending you a copy of a paper we presented at the Sept. 1996, Surface Mount International Conference. The paper is titled "The Effects of Solder Joint Voiding on Plastic Ball Grid Array Reliability". We performed a solder joint reliability study on BGA's with three levels of solder voids; no voids, nominal, and high voids. The PBGA's which had the high volume of voids, had improved reliability over PBGA's which had little to no voids. Solder joints with voids which measured 24% of the pad geometry, survived 16% longer than those solder joints which had no voids. Analysis, after temperature cycling indicated that the reliability improvement occurs because once a crack propagates to a void, it must re-initiate,in the opposite side of the void, to proceed further. This re-initiation causes a time delay in the total time it takes a solder joint to fully fracture. As a follow up to the 1996 study, we are presently temperature cycling (-40�C/+125�C) PBGA's which have void structures greater than 30% of the pad geometry. As of today, we have 1,630 cycles without a single solder joint failure. We continually monitor the solder joints under test, and will be able to tell when the first joint fails. Once temperature cycling, and analysis is complete, we plan on publishing the results. | | Any news re voids in BGA solder bumps. How does Mr. Burnette�s analysis and results (20-25 percent voids) working for uBGA/CSP�s. Regrads Ken Hedman

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