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Printed Circuit Board Assembly & PCB Design Forum

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Thermal Stress in Reflow

Greg Jones

#10005

Thermal Stress in Reflow | 23 August, 1999

I am looking for a rule of thumb regarding the maximum ramp standard components (chip capacitors) can tolerate without failure during the reflow process. The standard seems to be 3C\second, but this figure is generally derived from the average ramp rate a product experiences during reflow. Ex: A very light board spends 60 seconds in the first zone of a short convection oven, which is set to 150C, and is at 150C at the end of that zone. (Assume 30C ambient for simplicity) The averaged ramp rate for the zone would be 2C\sec--an acceptable profile statistic. But what is actually happening is the board is reaching 150C in the first 20 seconds of the profile, which gives an actual ramp rate of 6C\sec--well over any established rule of thumb. My question is: What is the ACTUAL ramprate, in Degrees C\second (and duration at degrees\second), that chip capacitors can stand without cracking, etc...

Thanks, Greg Jones

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Steve Surtees

#10006

Re: Thermal Stress in Reflow | 31 August, 1999

| I am looking for a rule of thumb regarding the maximum ramp standard components (chip capacitors) can tolerate without failure during the reflow process. The standard seems to be 3C\second, but this figure is generally derived from the average ramp rate a product experiences during reflow. | Ex: A very light board spends 60 seconds in the first zone of a short convection oven, which is set to 150C, and is at 150C at the end of that zone. (Assume 30C ambient for simplicity) The averaged ramp rate for the zone would be 2C\sec--an acceptable profile statistic. But what is actually happening is the board is reaching 150C in the first 20 seconds of the profile, which gives an actual ramp rate of 6C\sec--well over any established rule of thumb. | My question is: What is the ACTUAL ramprate, in Degrees C\second (and duration at degrees\second), that chip capacitors can stand without cracking, etc... | | Thanks, | Greg Jones | | I also have a similar problem - except the board material is only 0.8mm thick FR4 - I am concerned that the heating/cooling cycle of the thinner material is causing cracks in the solder joints?

Thanks

Steve Surtees |

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Dreamsniper

#10007

Re: Thermal Stress in Reflow | 31 August, 1999

| | I am looking for a rule of thumb regarding the maximum ramp standard components (chip capacitors) can tolerate without failure during the reflow process. The standard seems to be 3C\second, but this figure is generally derived from the average ramp rate a product experiences during reflow. | | Ex: A very light board spends 60 seconds in the first zone of a short convection oven, which is set to 150C, and is at 150C at the end of that zone. (Assume 30C ambient for simplicity) The averaged ramp rate for the zone would be 2C\sec--an acceptable profile statistic. But what is actually happening is the board is reaching 150C in the first 20 seconds of the profile, which gives an actual ramp rate of 6C\sec--well over any established rule of thumb. | | My question is: What is the ACTUAL ramprate, in Degrees C\second (and duration at degrees\second), that chip capacitors can stand without cracking, etc... | | | | Thanks, | | Greg Jones | | | | I also have a similar problem - except the board material is only 0.8mm thick FR4 - I am concerned that the heating/cooling cycle of the thinner material is causing cracks in the solder joints? | | | Thanks | | Steve Surtees | | | | It's not only the ramp rate that affects chip caps cracking...FR4 expands 2.5 times more than a ceramic capacitor. In my profile, my pre-heat ramps between 0.5 - 1.0 deg. C and i don't have any problem on my chip caps. Try playing with the conveyor speed and your oven zone temperature settings.

hope it will help !

Dreamsniper

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Reflow Oven

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