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Via Sizes

armin

#8446

Via Sizes | 23 November, 1999

I've got a 100mm X 70 mm Dense PCB...The via holes used is 1.0 mm some are under SOIC's ...what problems that this type of via design poses ?

all ideas are welcome !

thanks and regards, armin

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armin

#8447

Re: Via Sizes | 23 November, 1999

Is there a Standard/Guidelines that (or which IPC guidelines) defines the pad edge-pad edge clearance for Various via hole and component land sizes. Also defining why Vias shouldn't be placed under discrete components.

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cklau

#8448

Re: Via Sizes | 25 November, 1999

Via is normally a plated thru holes in (0.63 to 1.0 mm (0.025" to 0.040") diameter lands , which unless properly treated they must be located away from the component lands to prevent the solder migration off the component land during reflow soldering process thus causing insufficient solder fillets on components.

Via may be placed under the SMT component if they are to be reflow soldered.But if they are to be wave soldered , vias underneath component should be avoided or tented with solder mask cos during wave soldering of these assemblies , the flux might be potentially become trapped under these packages .For effective cleaning via may be located only on underneath of a SMT in full surface mount assemblies that would not be wave soldered.

No discrete component's should be mounted on untended vias or exposed conductive patterns because sometimes the body of these component especially the metal type will come contact with this element's.And the other thing is that sometimes untended vias may be required to be used as test target for bed-of-nails type probe(ICT) and/or rework ports and thus it is not wise to mount discreet component across these elements.

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