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Need advise on regarding Vias

armin

#8211

Need advise on regarding Vias | 13 December, 1999

Hi All

I have a 0.7 mm diameter hole for vias, what�s the minimum annular ring for this hole diameter? What�s the term unsupported and supported holes refer to in IPC-2221 9.1.2 Annular Ring Requirements?

I have a proto-type PCB (designed by our R&D), with 0.7 mm diameter via holes (excluding the land) with annular ring sizes of 0.25mm � 0.30 mm thus making the total diameter land to be 1.30 mm. The separation gap betwwen these holes from some of the pad edges of (some) the components were 0.25 to 0.30 mm only and some of these vias are located under SOIC�s and Descretes. The way I see them is that they pose a potential problem (solder wicking/bridging) during wave soldering because of the via land-to-component pad edge clearance which is only 0.25 mm to 0.30 mm. The previous boards that we use have 0.5 mm dia. vias with 0.15 to 0.20 mm annular ring (land) thus making the diameter land to be 0.80 mm to 0.90 mm and the via land-to-pad edge clearance is 0.3 to 0.5 mm. These boards are all okay during wave soldering since their diameter land are smaller than what the above new board has. Our R&D says that 0.70 mm drill hole is cheaper than 0.50 mm. So it is a cost reduction issue on its part. Is that the correct way of doing cost reduction if proven to be a potential problem for solder bridging and solder wicking? Another thing is that our boards are coated with SMOBC solder mask, are the vias of the proto-type board considered tented?

I�ve read IPC SM-782

Section 3.6.3.2 IPC-SM-782 Surface Mount Design and Land Pattern Standard (1993 Release)

3.6.3.2 Vias Within Component Land Pattern Vias are plated through-holes in 0.63 mm to 1.0 mm diameter lands. They must be located away from the component lands to prevent solder migration off the component land during reflow soldering. The migration will cause insufficient solder fillets on components..........

IPC-SM-782A which is the amendment of IPC-SM-782 (1996 Release) replaced the "Vias Within Component Land Pattern" to "Vias and Land Pattern Separation"

Referring to figure 3.24 of IPC SM-782A (1996 Release), the minimum clearance stated between the land of chip components and the pad of via holes is 0.50 mm compare to 0.25 mm of its 1993 Release.

I�ve contested that there�s a problem with the above PCB design on land edge clearance between the via and the component given with only 0.25 to 0.30 mm clearance also giving emphasis that with that kind of diameter land (1.30 mm) and clearance (0.25mm � 0.30mm), those vias should not be placed under discrete components and evn under those SOIC�s.

The reply that I got is: � We know where we are going, how about you?�

Need your good advise on this�all inputs are more than welcome.

Thanks and regards, Armin

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cklau

#8212

Re: Need advise on regarding Vias | 14 December, 1999

Hi All

I have a 0.7 mm diameter hole for vias, what�s the minimum annular ring for this hole diameter? Ans: Fur inner layers Min = .006" hole-pad annular ring ; inner pad dia - hole dia/2 For outer layers Min = .005" hole-pad annular ring ; outer pad dia - hole dia/2. For Inner & outer layers Min .008" clearanse to edges of drilled keyway slot.

If the designed annular ring is under the above mentioned min requirement then a "tear drop" may be added.

Designed annular ring is the difference between a pad & the corresponding drilled hole , divided by 2.In some cases due to drill wander the hole is tangent to the pad.So for these case manufactured annular ring will be = the thickness of the plated copper in the hole.

For more accuracy pls refer to your in hose PWB fab house capability.

Another thing is that our boards are coated with SMOBC solder mask, are the vias of the proto-type board considered tented?

Ans : Some are tented and some aren't.

Well it look's like you had a "industrial dispute" problem at your hand .Nothing more that I can say execept that if you had doubt after too much study of the "IPC Bibble" please refer to your PWB equipment capability and or fab criteria.

Good luck,

Regards.

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#8213

Re: Need advise on regarding Vias | 14 December, 1999

Armin: How ya doin� bud? CK gives good advice, but I'd like to take a bit of a different angle.

Q1. For 0.7 mm (0.027in) diameter hole for vias, what�s the minimum annular ring for this hole diameter? Depends on what you�re trying to do. For instance:

Pad To Hole Ratio. For example, determine the pad size to produce a minimum annular ring and avoid breakout:

Drill size |0.018 inch Fabrication tolerance|0.012 inch (or whatever your supplier says) 2 times the min. annular ring |0.002 inch Pad size|0.032 inch

Taking a different angle, two points are: (1) Minimum via pad diameters vary according to substrate thickness. (2) The ability to use vias as test pads is part of the reason for selecting via pad size and separation.

So for 1.57 mm (0.062") thick boards, our minimum via diameter is: 0.33 mm (0.013") and the pad diameter is 1 mm (0.033"). We prefer 1 mm (0.040") pads.

Q2. What�s the term unsupported and supported holes refer to in IPC-2221 9.1.2 Annular Ring Requirements?

Supportive (Supported) Hole. A hole in a printed circuit board that has its inside surface plated or otherwise reinforced. Unsupported Hole. A hole containing no plating or other type of conductive reinforcement.

Q3. The separation gap between these holes from some of the pad edges of (some) the components were 0.25 mm (0.009 in) to 0.30 mm (0.012 in) only.

We like a 0.50 mm (0.02") separation. The minimum separation is 0.25 mm (0.01").

Q4. Some of these vias are located under SOIC�s and discretes.

Locating vias under any component is bad practice.

Q5. Boards are SMOBC solder mask, are the vias of the proto-type board considered tented?

SMOBC (Solder Mask Over Bare Copper). In printed circuit board fabrication, when the final metalization is copper with no other protective metal and non-soldereable areas are covered with a solder resist. This tells you nothing about the type of solder mask. Solder mask types have different capabilities to tent vias, ranging from: wet film tenting vias well to dry film tenting vias OK to LPI (Liquid Photo-Imageable) tenting vias poorly.

Q6. Is this the correct way of doing cost reduction?

It�s a good way of reducing the cost of fabricated boards, but that�s not the only cost your company writes check for. The "correct way" depends on the company, it�s goals for product development expediency and cost minimization, and a bunch of other stuff.

First, let�s separate the issues. Via hole size selection affects board fabrication cost. Via pad size has (virtually) no affect on board fabrication cost, but does affect testability and board reliability. Feature separation has (virtually) no affect on board fabrication cost, but does affect manufacturability and testability. Use of SMBOC affects both board fabrication and assembly cost. Solder mask type affects board fabrication and may affect assembly cost, depending on component pitch and manufacturing processes.

If your R&D people truly "know where" they�re "going," they (1) shouldn�t keep it a secret from the rest of the company and (2) should be able to explain to manufacturing process and quality types how these proposed changes reduce the shipped cost of the product, while improving reliability, and get their "buy-in" to the approach.

My2�

Dave F

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Boca

#8214

Re: Need advise on regarding Vias | 17 December, 1999

Outstanding advice gentlemen!

To borrow Dave F's line "I'd like to take a bit of a different angle." Ie. a few wave solder specific issues

If this assembly is going over wave solder then avoid vias under passive components, it invites solder balls and flux entrapment under components.

If vias are clustered too close to QFP pads they can (will) conduct heat from the solder wave thru the fab to the lands and solder joints on the top side of the fab. This can partially reflow top side SM joints and causing weak and open joints. The weak joints probably will not be caught in electrical test but wait until field service to fail. We have proven this a few times on our production floor.

Dave, would this make 3 cents?

Boca

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#8215

Re: Need advise on regarding Vias | 19 December, 1999

At least!!! But we really can't have you throwing "your at least 1� worth." The rate for marginally useful information, disinformation, and compounded confusion has been set at 2�. When someone undercuts the market price for drivel, it hurts us all. Think of the future generations, our brother and sister drivelers, they need to be assured a living wage for thir pontifications.

Please go for the long ball or stay home.

Ta

Dave F

ps: There is no charge for the use of catch phrases when attributed

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Boca

#8216

A small waste of time | 21 December, 1999

What's this about a minimum wage for drivel? 1 cent is where it's at! Competetive preassure in the marketplace will improve the quality of drivel for all! That is unless the 'You get what you pay for' law is invoked, then high priced drivel will dominate the land.

Don't no body be pontificat'n, authorized pontifications can only be make in Italy.

Is the 'long ball' thing like -If you can't run with the big dogs, stay on the porch?

Boca

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