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Decoupling caps and PCB layout

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Decoupling caps and PCB layout | 10 August, 2016

I guess I've been somewhat ignorant when it comes to the finer details of pcb layout. Lately I've read a couple of books that try their best to lead me on the straight and narrow. Here is a couple of examples of a recent board of mine, and I have highlighted three of the decoupling caps. The MCU is a LQFP100 package and the caps are 100nF in 0402 packages. The vias connect to ground and power plane. he top cap (C19) is placed according to best practices (as I understand them). The other two are not. I haven't noticed any problems. But then again the board has never been outside the lab.

I guess my question is: How big a deal is this? As long as the tracks are short, does it matter?

The Vref pins (reference voltage for the ADC) also have a 100nF cap across them. Vref+ comes from an onboard TL431 shunt regulator. Vref- goes to ground. Do they require special treatment like shielding or local ground? My approach has always been to rely on an unbroken ground plane. A ground plane will have the lowest possible impedance, but this approach may be too simplistic for higher frequency signals. I've made a quick stab at adding local ground and local power under the MCU (The part is an NXP LPC1768 bought from running at 100MHz). The yellow bits are the decoupling caps. I'll look into paralleling caps. The local ground and power are connected to the GND layer and the 3V3 layer where indicated.

The local ground and power are made with polygons (pour). It's going to be a major rerouting job to minimize the length of the "tracks". This technique will limit how many signal tracks can be routed under and across the package.

Is this an acceptable approach?

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