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QFN PCB Pad no Drain Hole

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#68976

QFN PCB Pad no Drain Hole | 17 May, 2013

HI, We are facing problem of Dry solder due to QFN Grounding Solder not Drain out in Via hole. also No drain hole on PCBs now we have 15k stock. which is leading to massive Rework. We have Tried by minimizing Ground Square apertures. but no Improvement. Please suggest possible solution. thanks Shrikant

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#68980

QFN PCB Pad no Drain Hole | 17 May, 2013

There's not supposed to be any effin 'drain hole.' Where's you get that from? Read this: http://blogs.smtnet.com/smt/other/qfn-btc-design-guidelines-thermal-pads-etc/

BR davef

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#68983

QFN PCB Pad no Drain Hole | 17 May, 2013

Wait.... No drain hole? Well then how are you supposed to get all that pesky solder to pull down off the part??? Have I been doing this wrong for the last 20 years??

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#68985

QFN PCB Pad no Drain Hole | 17 May, 2013

I am familiar with TI's documents on QFN mounting. I do not have an X-Ray machine, so I worry about excessive voiding that could happen with using the thermal vias improperly. As a general rule-of-thumb, I print paste with a 25% reduction on the thermal pads to keep the part from floating. TI's recommendation of 0.3mm vias on a 1mm grid has me worried about scavenging, though I could accept that the holes are too small to scavenge much.

So, now to my question (using TI's documents)... Do the .3mm vias on a 1mm grid scavenge any significant amount? The recommended stencil cut (multiple windows) implies that the small vias do not scavenge.

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#68988

QFN PCB Pad no Drain Hole | 18 May, 2013

isd.jww: Comments are: * Current thinking has flux volatiles being the major contributor to voiding, not scavanging by via * I have no reason to think that 0.3mm via won't gladly accept solder. Plug them, if that's a concern. * If your concern is inadequate solder coverage on the thermal pads, just pop a couple of the QFN off the board using a beer can opener and check the coverage on the board and the component ... I'd guess that you have plenty of solder. People talk about reducing stencil coverage of the thermal pad by 50%. [Read papers in the link I provided in an earlier post on this thread]

BR, davef

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#68989

QFN PCB Pad no Drain Hole | 18 May, 2013

OK, I've now read all of the documents you referenced. The problem still remains regarding the thermal vias and how to minimize scavenging. All the docs acknowledge top and bottom tenting, and it's problems. TI says don't do it. Plugging is usually not cost effective for the quantities I see. So the problem still remains, when relying on TI's document (no tenting), how much scavenging will happen with the 0.3mm holes?

Cirrus's Ap Note at least states "... maintain a via diameter smaller than .3 mm. When using smaller vias, the surface tension of the liquid solder inside the vias is more capable of countering the force of gravity on the solder within the via."

Looks like there is no definitive answer, so I need to do some of my own testing...

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#68993

QFN PCB Pad no Drain Hole | 19 May, 2013

We are EMS. Later revisions and Other models are get Modified.

Now we have some remain Stock of Pcbs abd there end also. We have taken trial with Reduction in Apparatuses. But even small amount of solder paste at thermal Pad is causing QFN lift up. Is it Possible to put thermal Adhesive instead of Solder paste. which may help for thermal conduction and QFN will not get lifted up.

Thanks for reply for thread initiated. Regards Shrikant Borkar

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#69010

QFN PCB Pad no Drain Hole | 20 May, 2013

Did you try a thinner stencil? More pressure and speed in the printer? What size is the QFN? Maybe the aperture needs to have a + in the center?

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#69023

QFN PCB Pad no Drain Hole | 21 May, 2013

What size QFN? What stencil design and thickness are you using.

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#69040

QFN PCB Pad no Drain Hole | 22 May, 2013

We do a lot of these devices and I guess I am not familiar the term "Dry Solder". The QFN device is not designed to have a drain hole, but needs to have thermal vias to control heat in most cases. We have used every possible gnd pad design and modification known to man and you can get better results with these mods, but a solder paste that is designed for low voiding and a solid square deposit with a 10-20% reduction in the center has worked the best for us. The voiding will never go away and really you dont want it to, there is a necessity for voiding in the gnds of these devices, but your Customer may want a certain amount of contact area on the gnd. (usually 79% if your Customer cares) The voiding that you are looking for should be many small voids almost like champagne bubbles.What you dont want is large Voids that constitute a high % of the overall void area. As an experiment you might try taking a device and tinning it and then wicking it semi-flat (this isnt that critical) and then flux the device place it and reflow. The results should be pretty good, especially the voiding. I want to warn you about surface finishes not too long ago we had a almost similar issue the voiding was huge and we couldnt get the device to sit flat on the PCB? The issue was that the surface finish was hard gold and the solder just wouldnt wet to the PCB causing the Gnd to be raised off the PCB to the extent that the I/O pads couldnt reach the PCB. New ENIG Surface finish has solved that issue and we are building 5 or 10k of that product a week.

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#69042

QFN PCB Pad no Drain Hole | 22 May, 2013

Also, I was just thinking that most of the large companies we work with do not consider via drain an actual void. As a matter of fact our high dollar super fantastic Xray system actually has a switch to turn off the vias during void detection so that they are not considered in the overall void % calculation. If you considered this would you still have an issue? Also just remember after you solve this 1 there will be another, and another...all have different designs under that QFN you will experience failure 1 day and perfection on the next..its the nature of our business and thats why we do it...the challenge!

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#69122

QFN PCB Pad no Drain Hole | 31 May, 2013

hI

Dear all I am Attaching herewith Pics for ok one and Bad- Pad. I hve tried to reduces Stencil apparatuses , results are satisfactory by 30 %

Attachments:

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#69126

QFN PCB Pad no Drain Hole | 31 May, 2013

Is this a "thermal balance" issue? In the 2nd image you have a group of pads blobbed together as one giant pad. IMHO this is a bad idea, QFN's rely heavily on the magic of your paste and good PCB design to get good alignment. When your solder paste is melted, the tension could be pulling that device to the right, a good amount of the paste will do the same. How is this group of pads cut on the stencil?

Also what is this PCB finish?

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#69133

QFN PCB Pad no Drain Hole | 31 May, 2013

With regards to first picture.(Large themal vias) I would attempt to measure the area of the ground pad, less the area of the "drain" holes or Thermal Vias. From that result I would reduce the aperture to account for about 50% coverage of that remaining area. We have used these large thermal vias as an inspection point, in that wetting to the PWB can be observed through the via from the backside. Use a grid pattern for your apertures for improved outgassing during flux activation.

The other picture (small Thermal Vias) I would do a straight up 35-40% reduction in printed area, and use a grid pattern to help with the outgassing during the flux activation stage.

These really shouldn't be that tough. And as always, solderability is king. Re-tinning of these parts prior to use has also been utilized in cases where we can't get the voiding out through normal processes.

Just my $.02, but based on a history of fair success. 'hege

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