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SMT electronics assembly manufacturing forum.


Solder Paste layer question

Views: 3790

#67695

Solder Paste layer question | 29 November, 2012

I was asked a question; if you are doing a DFM on a solder paste layer what do you look for? it stumped me

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#67697

Solder Paste layer question | 29 November, 2012

When you say "solder paste layer," what are you talking about: * Post-print / pre-placement quality inspection * Post-reflow solder inspection * er what?

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#67699

Solder Paste layer question | 30 November, 2012

What is DFM? Design for Manufacturability?

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#67700

Solder Paste layer question | 30 November, 2012

checking the solder paste layer what is suggested in order to perform a robust DFM

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#67701

Solder Paste layer question | 30 November, 2012

I take that as a no, you have lost me

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#67702

Solder Paste layer question | 1 December, 2012

Do you mean the Paste Layer of the Gerber files? If so then you can check for aspect and area ratio of the component apertures (which is determined by the thickness of the stencil) there is an IPC specification for this and it is IPC-7525A I believe. There is also software that can do this for you. If you are interested in that type of analysis. Best of luck in you endeavor.

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#67709

Solder Paste layer question | 2 December, 2012

Where might I obtain this software that performs the aspect ratio for stencils, I could use Excel but why reinvent the wheel if there's something better

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#67714

Solder Paste layer question | 3 December, 2012

Well there are 2 ways to go about this, the first would be to have your stencil provider do the calculations for you (with his software) or you can purchase LPKF CIRCUITCAM EDIT from LPKF. This is a Gerber editing software that is designed to make stencil files for laser cutting.This is not the same product as Aegis CircuitCAM.

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#67794

Solder Paste layer question | 8 December, 2012

Mentor(Valor) has dfm softwares that not only looks at the stecnicl layers buy can look at other impacts that could effect the optimisation of the stencil design, ie solder mask layer tolerances defined from fabricator-design etc - this is a upper end solution.

Also they have stencil optimiser tool as part of their MSS Process Preparation Tool Suite - can run templates, run a aspect ratio check and highlights potential issues per device package etc....

Just some ideas to add to your thoughts

Can do manually with Gerber CAM based editors etc but the above tools potentially more wholistic if approach.

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