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Bottomside SOT23 opens & DOE test board layout


K

#6689

Bottomside SOT23 opens & DOE test board layout | 24 May, 2001

Hi All:

We�ve got a problem here with opens on bottom side wave soldered SOT23s. Based on past experience and review of the SMTnet archives, I feel that our main problem is pad size. We have the same size pads for bottom side SOT23s as we have for the top (which is .035� by .035� with .080� between the single pad center to the double pad center).

I�m going to design a test board that we can use in running a DOE to see what would be the optimal pad size to reduce/eliminate opens on these components, but not consume any more real estate than necessary.

While I�m at it I�m going to play with pad sizes for 0402s up thru 1206s as well as some different SOICs. Since we have a standard pallet size here, I�ve got all kinds of real estate (8.3� x 11.25�)

I was wondering if anyone out there, who has been through this before would have any advice on things to be concerned with while laying out this test board.

TIA;

Kelly

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#6692

Bottomside SOT23 opens & DOE test board layout | 24 May, 2001

Try: * Poor looking solder connections * Good looking solder connections * Reliable solder connections

Look to Ch 5 of "Manufacturing Techniques For Surface Mounted Assemblies"; RJ Klein Wassink & MMF Verguld; Electrochemical Pub; ISBN 0-901150-30-4 as a point reference.

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