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ICT and specifying PCBA testing

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#61439

ICT and specifying PCBA testing | 23 March, 2010

Since I'm new to the forum I probably ask previously answered questions (that I have not found) but I would be grateful if someone could clarify this for me.

I'm in R&D at a company where we design low volume (1k-10k) fairly complex PCBAs for our products. We do inhouse CAD closely following PCBA suppliers DFX guidlines. Now I'm looking at testing at our PCBA supplier

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From my perspective what we want from the PCBA supplier is:

(1) Correct mtrl (PCB and comp according to our spec/BOM)

(2) Solder and components placed in the correct positions on the board

(3) All solder joints ok (IPC610D level 2)

(4) No out-of-spec stress to PCB or comp (main concern heat)

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In volume production I can see the following methods/tests to achieve the above points

(1) with good procedures and systems at the PCBA supplier

(2) with AOI

(3) with AOI, (inline) x-ray, cutting PCBA samples

(4) with good procedures and systems at the PCBA supplier

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What good does ICT, JTAG testing do as complement to the above? Find screw-ups in (1)? Additional test coverage in (2)?

What other methods are there to verify (3)? Capacitive probe testing?

BR

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#61458

ICT and specifying PCBA testing | 24 March, 2010

So, your contractor has those BIG hunks of metal in the other room and is trying to get their utilization up by selling you fixtures and software. Hmmm ... He should give you that stuff for free just to demonstrate to you how superior their process is compared to other CMs.

Over time, the trend in manufacturing defect detection has been: * Prehistory => Ignore the defect * Late 1990s to early 2000s => ICT * Early 2000s to mid-2000s => MDA * Mid-2000 on-ward => AOI

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#61467

ICT and specifying PCBA testing | 25 March, 2010

When testing components on a PCBA, try to validate coverage for presence, correct, orientation, live, and alignment. AOI is not really great at catching cold solder joints and damaged components, and from my experience an X-Ray is only as good as the human eye that is operating it. ICT offers good diagnostics in a short period of time.

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#61481

ICT and specifying PCBA testing | 26 March, 2010

I have been using ICT for a number of years. It is still a viable resource for catching defects in the production process. AOI doesn't catch everything, such as bridging on QFN or J-lead devices (this will depend on the type of AOI and camera system you have). Of course, the primary advantage ICT has over AOI is electrical testing. Most of your component placements will be tested and caught, if there is a defect, with your AOI; however, there are hundreds of potential production defects (i.e. faulty parts, pcb etching errors, lifted leads, solder side shorts etc.) that will escape the AOI (again, your coverage will depend on your AOI capabilities). Once at functional, it may fail, but it will also be harder to track down minus an ICT. Given, if your process is such that it is very reliable, you may not need it, but it does give you a peace of mind, and supplements the AOI perfectly, that your builds are to specs. Once you think you don't need it, you will.

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#61483

ICT and specifying PCBA testing | 26 March, 2010

Thanks for your replies!

So what I understand is that ICT in reality is "only" a production process safety net, but it's a net that in most practical cases is needed.

What ICT can not catch is (all) bad solder joints. What are the methods to find them? - Capacitive probe testing (TestJet)? - X-ray? Is not in-line x-ray images inspected by automated image processing?

BR

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#61497

ICT and specifying PCBA testing | 29 March, 2010

Test Jet will work for catching lifted leads, certainly. X-ray is the only thing for testing for internal solder defects such as voids and cracks. I personally do not have any experience using X-ray, so I cannot advise on its reliability. Perhaps other members can chime in. All I know is what I've read.

What I can do is speak on my experience with AOI. For catching solder defects such as deficiency or lifted leads, it depends on what type of camera system you have, and the light sources available. For systems with a top-down only camera, there are algorithms available such as test tip gray and pattern matching that can catch some of these defects; however, the success of these algorithms vary and may be inconsisant. There are systems with side-angle cameras that might provide better visibliity for lifted leads, but these cameras are used primarily for solder inspection of QFN and J-leaded devices and again, the success for catching lifted leads may vary. I would advise the use of ICT in conjuction with AOI. Both are valuable resources and can test various defects that the other cannot. Test Jet (much like FrameScan on the Teradyne systems) is a reliable tool used on Agilent systems for testing connectivity of leads. I would recommend this approach for testing this defect.

I did not understand your last sentence. "Is not in-line x-ray images inspected by automated image processing?"

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#61503

ICT and specifying PCBA testing | 30 March, 2010

Regarding X-ray I was referring to ssager's comment "...X-Ray is only as good as the human eye that is operating it...". I thought x-ray images could be checked by software algorithms to find defects, not only human eye?

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jw

#65339

ICT and specifying PCBA testing | 1 November, 2011

With TestJet technology, if we want to test a 64 pin BGA, would we need probe access to each net of the device to get full coverage? If not, would I only get coverage to the pins that have probe access? In a nut shell, How exactly does it work?

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#65340

ICT and specifying PCBA testing | 1 November, 2011

Agilent TestJet Technology White Paper

In the early 1990s, the testing of digital parts became problematical. Previous in-circuit test techniques sought to ensure a correct, functioning part by applying digital patterns, called vectors, to the inputs of the device, and monitoring the outputs of the device. If the outputs matched the expected patterns, the digital part was deemed to be the correct part, oriented properly, and soldered properly. This technique had two requirements that became difficult to supply by the mid-1990s:

Knowledge of the functioning of the digital part so that an appropriate set of patterns could be generated; and test probe access to every input and output of the device.

The Agilent TestJet technique was patented and introduced by Agilent in 1994 after several after several years of research and refinement. It makes use of a property of most digital ICs in use in the mid-1990s: the lead frame, a metal framework that includes the devices input, output and power pins and their extensions up to the point where the silicon die is attached. The size and shape of the lead frame is fairly stable from device to device and vendor to vendor.

The technique uses an external plate, suspended above the digital part, and separated from the lead frame by the plastic or ceramic material of the device housing. The lead frame and the external plate form a small capacitor that can be measured by stimulation with an ac source. Each pin (inputs, outputs and power) consists of a part of the lead frame, and so each can be detected as a separate capacitance.

The property that makes this technique interesting for in-circuit test shows up when a device pin is not properly soldered to its trace on the board. In this case, there is an additional capacitor in series with the TestJet capacitor. This additional capacitance exists because there is a tiny air gap between pin and trace. This is a very small capacitance, much smaller than the TestJet capacitor. The series combination of the TestJet capacitor and this additional pin capacitor is smaller than either capacitor. So, the TestJet technique seeks to measure the capacitance at each device pin, and identify each pin that is significantly smaller than an expected (computed) value. A threshold value can be set for each pin to discriminate between well- and poorly-soldered connections.

The big advantage of the Agilent TestJet technique is that no knowledge of the core functionality of the device is needed. The technique depends only on physical properties of the packaging. It still requires test probe access to all device pins.

Agilent takes advantage of a particularly stable and low-noise analog measurement system in the Agilent 3070 systems to measure capacitance in the 0-200 femtofarad (1 ff = 10-15 farads) range. There is sufficient repeatability in the measurement to permit excellent discrimination between good and bad solder connections.

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#65482

ICT and specifying PCBA testing | 18 November, 2011

As the article eludes to, you still need probe access to measure the pins with TestJet. One thing I wanted to add was the use of JTAG for use with Boundary Scan. Certain devices have JTAG capability, but not all JTAG devices are Boundary Scan compatible. This is unfortunate, but more and more devices are being supported with Boundary Scan. This allows you to daisy-chain your JTAG ports together and test the I/O properties of the device; thereby, testing for lifted leads as well, if you choose, but complete access is not required. That's the benefit of Boundary Scan, you only need access to the JTAG port. Each I/O pin has a cell that can be tested for proper operation. JTAG then reports where errors occurred in the chain. You could have many devices chained together for testing. This could be supported on your ICT or for use on the bench. Using without probe access however only tests the device, not the bond between pad and lead.

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