Low Voltage Device damage on z18xx ICT| 25 November, 2008
We are using z1850/60 machines. The APC test is damaging a 1.8V device on the board. The APC stimulates -/+3Vdc in fast mode. I understand the dangers of over-voltage. But what I need to know is how the part is being damaged when the entire board is floating from system ground? Is it possible the device is being powered during the APC test? I have found that removing node 0 (board ground) fixes the problem. This would lean towards a power up issue during this passive test. However I am not sure why. Does anyone have any experience with 1.8V logic on the z18xx systems or any other systems for that matter. Thanks for any assistance you can provide.
Low Voltage Device damage on z18xx ICT| 26 November, 2008
Investigation of Device Damage Due to Electrical Testing, R Croughwell & J McNeill, Worcester Polytechnic Institute Abstract: This paper examines the potential failure mechanisms that can damage modern low voltage CMOS devices and their relationship to electrical testing. Failure mechanisms such as electrostatic discharge (ESD), CMOS latch-up, and transistor gate oxide degradation can occur as a result of electrical over-voltage stress (EOS). In this paper, EOS due to electrical testing is examined and an experiment is conducted using pulsed voltage waveforms corresponding to conditions encountered during in-circuit electrical testing. Experimental results indicate a correlation between amplitude and duration of the pulse waveform and device degradation due to one or more of the failure mechanisms. [http://www.teradyne.com/atd/resource/docs/testStation/tpWPI.pdf ]