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via as test point



via as test point | 26 February, 2001

I'm working a problem and looking for your input. Here the deal: Two sided mix technology board. Test is using unmasked via points on bottom for test points. Our fab drawing states tent via points on top side. First set of board came in with no tenting making the vacuum fixture at test nonfunctional. Second set of board came in with "plug via" and for some reason this was not good for test either. Test want the stencil modified to put past on each via to accommodate connection of the test fixture to the board and giving vacuum seal. When I ask if using via points as test points is unusual, the reply I get is no. In my experience I have not seen a stencil with .040" holes for via pasting, and fear that there will be a clogging problem. I'm very reluctant to add these apertures and complicate my stencil pasting operation. Why cant the board house build the board as specified? Have you seen via as test point? Are the pasted?

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via as test point | 26 February, 2001

First, I don�t understand why your board fabricator can�t do a good job plugging your vias. Additionally, when you consider that they forgot to plug the first batch of boards, it makes me wonder if they are desirable as a supplier.

Generally, we use "via in pad" (VIP) to allow test assess on the bottom side, as you discuss. VIP requires a controlled process by the fabricator. Specify no plugging [or tenting] and a via "open-ness" requirement and it�s consistency to the fabricator. [This is already starting to sound dicey, when you consider a fabricator that can�t remember to plug a via.]

VIP requires careful sizing of the stencil apertures [and pads] to prevent insufficients when the hole is at its maximum size, yet allow no excessive solder when plugging a minimum size hole. In some cases, VIP forces use of step-down stencils and that at times forces use of non-metal squeegee blades.

If you don�t clean after surface mount, the flux from the paste can flow to the bottom surface of the test pad, resulting in test probing problems. Even if you clean after SM; but then wave the board, additional residues may be released from the via during that process. This again causes ICT nightmares.

Think about "optimizing" your paste, ICT probes, ICT fixtures, etc. in order to minimize the test issue. Generally, once the assembler resolves one set of issues, the designers use VIP technology on new features that require additional process engineering development. For instance, shared vias on the top and bottom sides, or VIP's on very small feature such as 0603 pads, so that compensating with a larger stencil becomes a problem.

All the issues with VIP are compounded with thicker substrates (GT 0.062"). In the end, VIP is a designers friend and an assemblers nightmare. If you can control it such that only certain large features on 0.062" or less thick boards use VIP's, it can be tolerable. Otherwise the added effort (engineering, test, inspection) makes it better to avoid.

Consider that it may be best not to start down this slippery slope. Consider blind microvias that only go down one layer be used in place of VIP. The designer can get his added functionality and the assembler should not see issues. Of course, you need a PWB fabricator capable of reliably providing this for you. [Ooops, we�re back to that again!!! You�re sunk!!! Glub, glub.] ;-)

I'm not current on this, but IPC has begun [finished??] such an effort. The Plugged Via Performance Task Group (D-33d) "will develop acceptance criteria for protecting plated-through holes, blind and buried vias. The work of this task group will be [has been] submitted to the Rigid Board Performance task group for inclusion in the IPC-6012 B Revision." [Maybe some can status us on this effort.]

Finally just to cloud the issue completely, a study done [in the distant past] by Roger Wild at IBM showed that an unfilled via was most reliable, a completely filled via was almost as reliable as an unfilled via and a partially filled via was not at all reliable. Roger's study was conducted by subjecting PWB�s to several thousands [I think] fairly stringent thermal cycles and monitoring for both an increase in resistance and an open circuit.

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