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Voids problem in Lead free process

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Voids problem in Lead free process | 5 October, 2006

Hello all,

We have problem with voids in one of our product.

We are soldering IC (package SO8) with under the components grounding connection. The ground pad for this component has 3 via holes (before producing we have to cover this 3 holes from bottom side of PCB by Kapton tape -by the way do you have any ideas how to do this).

After lead free process (reflow oven 7 zone top bottom heating without nitrogen) we found big area of voids under this componets (ground connection).

How we can remove this situation and does via holes (cover from bottom side by Kapton tape) keep the air entraped during printing and making problem during reflow?

The PCB was designed for leaded process but customer doesn't want to change anything yet. We have to cover this via due to the fact that PCB is flex board 0.3 mm thickness and all solder is dissapering. The ground connection has to be very good due to the fact that PCB is desing for high frequency.

Regards David

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Voids problem in Lead free process | 5 October, 2006

with this design you will have voids, you cannot trap the gas inside of via it has to go somewhere. These vias should be relieved from pad to prevent the scavenging of the paste during reflow. You may try a thicker stencil if you can to allow for the extra solder being scavenged by vias.

May want to try soldering via location instead of tape (prefill with solder).

Bottom line is it needs redesign.


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Voids problem in Lead free process | 5 October, 2006


We have seeing this more and more in the recent weeks. In a nut shell, yes; we believe that the voids that you are seeing are from the trapped air in the via from printing over it. If you could remove the Kapton tape, this might help. Also, if the via is large enough, you can try not printing over the via.

Another approach that you might want to try is increasing the time above liquidus (TAL) and Peak Temperature. This will lower the surface tension of the alloy and allow for the air to escape. More information can be found at

I can also look over your profile and make other recommendations. Should you have any further inquiries, please don't hesitate to ask. My contact information is below.


Mario Scalzo, SMT CPE Technical Support Engineer - Southwest Region 315-853-4900

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Voids problem in Lead free process | 6 October, 2006


Thank you for your comment.

I will try to increase TAL and check what is the differnces.



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matt kehoe


Voids problem in Lead free process | 13 October, 2006

Try this.Might be a solution.

mk 770-475-4576

This message was posted Add this forum to your site! Click to learn more. the Electronics Forum @

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Voids problem in Lead free process | 26 October, 2006

First, Voiding under thermal pad is unavoidable(pardon the pun), unless you can find a way to add sufficient amount of solder paste to cover the area, and match that solder volume on your terminal leads. I build HVM qty's of "QFN" components w/ thermal pads(ground pads)under the body of the part, and we typically see between 40-65% voiding. Unfortunately it is very difficult to reduce, and not possible to eliminate. We did incorporate a new ground pad design on our PCB which has greatly improved coverage of the ground pad. It consists of using small squared on the PCB using Solder Mask to greate this small squares, and then overprinting on these small pads to get suffcient paste under the pad to reduce voiding. Be careful not to over do it, or you may see part floating. One other suggestion: Have the component supplier of this part, perform a thermal analysis w/ different void%(solder coverage), to determine what the thermal impact is for different levels of voiding. You may be surprised at how little voiding can impact thermals/grounding

2nd, As far as via's under the ground pad. We do this, but we use fairly large vias, to assit w/ air flow, and heat dissipation Hope this helps...

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