QFP IC open solder

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I got one problem from my production line recently. One 0.5m... - Sep 21, 2002 by Machine

Sometimes the cut end of QFP leads have corrosion that is ve... - Sep 22, 2002 by davef

We encounter this problem also , I know that it 's acceptabl... - Sep 23, 2002 by FRANKY

Comments are: * It�s interesting, but not surprising that y... - Sep 23, 2002 by davef

Hi, In your message ou talk about the QFP toe, we hav... - Sep 24, 2002 by

Although focusing on solderability may be the right answer, ... - Sep 24, 2002 by dragonslayr

Stencil cleaning process is taking by machine every 15 board... - Sep 28, 2002 by Machine

Machine

#21679

QFP IC open solder | 21 September, 2002

I got one problem from my production line recently. One 0.5mm pitch QFP IC have been used on my PCBA. Actually, the defect was happened in randomly. Sometime, we got the fillet completely but sometime is not. The solder joint look like is good, but the join is open. On the other hand, we found the lead of the IC is not complete coating on the cutting edge. Anyone can help me on this problem?

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davef

#21681

QFP IC open solder | 22 September, 2002

Sometimes the cut end of QFP leads have corrosion that is very difficult to solder. If this is what you're talking about, it is not a defect according A-610C, 6.5.2, Exposed Basis Metal

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FRANKY

#21684

QFP IC open solder | 23 September, 2002

We encounter this problem also , I know that it 's acceptable per IPC standard but sometime it fail at ICT and FCT , then this problem should be prevent , we found it with QFP 16 mil pitch and the defect looklike negative wetting at the front of lead but we found only one side of QFP in random lead , we try to measure temperature profiling at 4 side and found that it 's different about 3 sec.( at 183 dC ) then I try to reduce the time diferrent from 3 sec to 1 sec. and can release the defect about 4-6% ( before adjust defect about 5-7% ,after implement defect about 1-2 % ) but I cannot 100 % prevention (not use N2 ) , and I think it should be better if you can run under N2 condition because this defect may from re-oxidation at preheat zone. Anyone have better experience please suggestion ?

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davef

#21714

QFP IC open solder | 23 September, 2002

Comments are: * It�s interesting, but not surprising that your time above liquidous varies around the sides of this component. * You are correct in thinking that it is better to reduce than to increase the temperature differences around the component. * It�s possible that N2 could help your solder wetting, but that would vary according to the source of this problem. * Originally on this thread, we were talking about poor soldering of the toe of a QFP, but the problem you have is different than that problem. The area of your wetting problem is larger than the toe of the component lead. Your problem could be cased by a range of things [ie, connector lead solderability, pad solderability, low activity flux, insufficient paste deposition, poor placement accuracy, etc] that could be in addition to setting the proper heating recipe for your oven that you�ve been talking about here.

Focusing on your question about your reflow recipe, rather than focusing on trying to minimize the differences in time over liquidous on various sides of this component, consider profiling and setting temperatures on that one side of the component that is giving you fits [the one where you see the poor wetting] and letting the temperatures on the other sides of the component pretty much fall where they fall.

Finally, if you think there could be issues affecting the wetting of your component that are broader than the recipe issues that we�ve been talking about, understanding more about the situation would help us make a contribution.

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Yannick

#21716

QFP IC open solder | 24 September, 2002

Hi,

In your message ou talk about the QFP toe, we have some problems with that in our facilitie, Do you have some ideas to solve thise kind of problem?

Thank You

Yannick

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dragonslayr

#21727

QFP IC open solder | 24 September, 2002

Although focusing on solderability may be the right answer, I wonder if you are satisfied that co-planarity is not the root cause. With random events of contact opens, this may be the case.

Cleanliness of the stencil can also be a source of your problem. Are you very sure that your stencil apertures are not clogging or building up paste that prevents the intended volume to be printed? How often are the stencils wiped? Every board? Every 4 boards? Are your stencils cleaned in an ultrasonic cleaner periodically? If so, how often?

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Machine

#21786

QFP IC open solder | 28 September, 2002

Stencil cleaning process is taking by machine every 15 boards. We are using wet, vaccune, Dry, Dry cleaning process. The aperture of the stencil is fullfil the aspect ratio.

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