SOIC solder thieves vs enlarged trailing pads

Hello!

Does any one know of a disadvantage of using the Phillips recommended wave solder SOIC footprint where the last pad on each side of the SOIC is enlarged, instead of placing an extra pair of pads behind the SOIC. Both footprint patterns seem effective in eliminating bridging on wave soldered SOICs (especially if the trailing pad or solder thief pad is at least 3 times as big as the normal SOIC pad). Thanks for the insight.

Ted

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