best lands for a DFN20 Intersil RTC, cleaning

The ISL12020 real time clock comes in a 20 lead DFN, and includes a 32kHz crystal in the package. The terminals of the crystal and oscillator come out to external pads and are highly susceptible to leakage to the neighboring power supply pins. With too much leakage, the clock stops. There are large pads under the center of the chip that kick out a lot of flux and restrict the path for cleaning under the chip. Our CM has had trouble with it, and it has caused trouble later, after deployment, especially at elevated humidity.

I've discussed this at length with an FAE at Intersil, and it turns out that some of the pads on the chip are not connected internally, He has suggested leaving paste off of those lands, and even leaving off the lands completely, in order to reduce the amount of flux and to open up a path for cleaning. He was not sure however about the effect this would have on how the chip rides up on the solder paste. That is what is bringing me here.

Link to the part at Intersil: http://tinyurl.com/q5gwfom Link to data sheet land pattern:http://tinyurl.com/ov293of Link to new suggested lands:http://tinyurl.com/ofle2fh

On the new version (also attached), we would leave off the lands shown in light red which are the "do-not-connect" pads anyway. There is no thermal purpose for the large central pad. Solder paste coverage would exactly match the dark red areas.

Issues with this plan? I'm concerned about having more coverage at one end of the chip than at the other.

The solder paste is leaded Alpha WS-916, water soluble, but later we will also build this board lead-free.

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